FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Same Nios Code But Slightly Different FPGA


I am using a Terasic DE0 Nano with a EP4CE22F17C6 device. I use the GUI based tools for much of the work, but I am trying to transition to command line tools to automate the overall build process.

I have an FPGA design that has four slightly different variations. The Nios code sees the same hardware/software interface for them so the C code does not need to change. As of now, I am maintaining separate FPGA and C code bases for each of the FPGA variations so that the Eclipse tool does not pitch a fit about the wrong BSP being used for the software. Obviously, this is a bad solution and I would like to change it.

Here is my question - 

Assuming I ensure that the C code is compatible across all four FPGA variations, can I just pick the desired FPGA HEX file when I generate the JIC file for a given FPGA variation?

Are there any subtleties I need to be aware of here?

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Hi Jeffery!


First of all, thank you for reaching us.


Regarding your question, it is possible, you can take a look into the following links to see how to do it properly.



-Eliath Guzman