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5283 Discussions

Shift Register to RAM inference

eamun1
Beginner
260 Views

Hello,

 

I'm wondering what would be the requirements for the compiler to be able to infer shift registers to ram?. I instanced the template from quartus template but this is using FF instead of ram memory. My FPGA is 10CL080YF780I7G:

 

-- Quartus Prime VHDL Template

-- Basic Shift Register with Multiple Taps

 

library ieee;

use ieee.std_logic_1164.all;

 

 

entity basic_shift_register_with_multiple_taps is

generic

(

DATA_WIDTH : natural := 8;

NUM_STAGES : natural := 56

);

 

port 

(

clk : in std_logic;

enable : in std_logic;

sr_in : in std_logic_vector((DATA_WIDTH-1) downto 0);

sr_out : out std_logic_vector((DATA_WIDTH-1) downto 0)

--srvector : out std_logic_vector(NUM_STAGES*DATA_WIDTH-1 downto 0)

);

 

end basic_shift_register_with_multiple_taps;

 

 

architecture rtl of basic_shift_register_with_multiple_taps is

 

-- Build a 2-D array type for the shift register

subtype sr_width is std_logic_vector((DATA_WIDTH-1) downto 0);

type sr_length is array ((NUM_STAGES-1) downto 0) of sr_width;

 

-- Declare the shift register signal

signal sr: sr_length;

 

begin

 

process (clk)

begin

if (rising_edge(clk)) then

--if (enable = '1') then

 

-- Shift data by one stage; data from last stage is lost

sr((NUM_STAGES-1) downto 1) <= sr((NUM_STAGES-2) downto 0);

 

-- Load new data into the first stage

sr(0) <= sr_in;

 

--end if;

end if;

end process;

 

end rtl;

 

 

 

0 Kudos
1 Reply
RichardTanSY_Intel
180 Views

The instantiated template is slightly different from what I get:

Please refer to the below code.

 

library ieee;

use ieee.std_logic_1164.all;

 

entity basic_shift_register_with_multiple_taps is

 

generic

(

DATA_WIDTH : natural := 8;

NUM_STAGES : natural := 64

);

 

port 

(

clk : in std_logic;

enable : in std_logic;

sr_in : in std_logic_vector((DATA_WIDTH-1) downto 0);

sr_tap_one : out std_logic_vector((DATA_WIDTH-1) downto 0);

sr_tap_two : out std_logic_vector((DATA_WIDTH-1) downto 0);

sr_tap_three : out std_logic_vector((DATA_WIDTH-1) downto 0);

sr_out : out std_logic_vector((DATA_WIDTH-1) downto 0)

);

 

end entity;

 

architecture rtl of basic_shift_register_with_multiple_taps is

 

-- Build a 2-D array type for the shift register

subtype sr_width is std_logic_vector((DATA_WIDTH-1) downto 0);

type sr_length is array ((NUM_STAGES-1) downto 0) of sr_width;

 

-- Declare the shift register signal

signal sr: sr_length;

 

begin

 

process (clk)

begin

if (rising_edge(clk)) then

if (enable = '1') then

 

-- Shift data by one stage; data from last stage is lost

sr((NUM_STAGES-1) downto 1) <= sr((NUM_STAGES-2) downto 0);

 

-- Load new data into the first stage

sr(0) <= sr_in;

 

end if;

end if;

end process;

 

-- Capture data from multiple stages in the shift register

sr_tap_one <= sr((NUM_STAGES/4)-1);

sr_tap_two <= sr((NUM_STAGES/2)-1);

sr_tap_three <= sr((3*NUM_STAGES/4)-1);

sr_out <= sr(NUM_STAGES-1);

 

end rtl;

 

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