Stratix 10 GX L-Tile Dev Kit Resource compiling Issues

[seanchen1996]

Hi ,

I'm having trouble compiling the resource files of Intel® Stratix® 10 FPGA's .

The following URL:

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx.html

I couldn't compile the project of resource files that occurred error as following figure

There is my compiling environment :

What kind of environment do I need to compile this project?

Thanks.

[RichardTanSY_Intel]

This might be related to this KDB:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074366.html

You may check out the reason why Error (329006): Some pins have illegal board trace models happens and action to take.

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/esin_pins_with_invalid_board_trace_model.htm

Let me know if it helps.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[RichardTanSY_Intel]

May I know does my latest reply helps?

Regards,

Richard Tan

[RichardTanSY_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.