Stratix 10 SOC FPGA LVDS

[kiransr]

Hi,

We have LVDS clock & data signal coming from ASIC to stratix 10 SOC FPGA, can we use these signals without any clock recovery logic directly or not

Regards,

Kiran

[FvM]

Hi,

if you need clock recovery depends on the kind of input signal. A signal comprised of data, bit clock and frame clock, e.g. ADC output doesn't need clock recovery. In any case, there are no LVDS decoding features inside HPS. They have to be implemented in FPGA fabric, data would be transferred to HPS through a bridge.

[AqidAyman_Intel]

Referencing the user guide, the soft clock data recovery (soft-CDR) mode is useful for asynchronous clocking applications.

[AqidAyman_Intel]

I wish to follow up regarding this thread. Are there any more supports needed? If yes, please let me know before I close this thread.

[AqidAyman_Intel]

I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.