Stratix V Development board with QSFP ports

[Altera_Forum]

Hi, 

 We have just bought a Bittware S5-PCIe-HQ development board which has a Stratix V FPGA.  On the board are 2 QSFP+ ports. We wish to use these ports to transmit and receive data to and from the FPGA (probably using an Ethernet interface) but we don't know where to start.  I don't have too much of knowledge of FPGAs but if anyone has knowledge of this or can point me in the right direction it would be much appreciated.   Thanks, Paul

[Altera_Forum]

Hi Paul, 

  --- Quote Start ---   but we don't know where to start.    --- Quote End ---   Start by reading about the transceiver toolkit and synthesizing a design using a Stratix V, eg., Altera's examples are here  http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html    --- Quote Start ---   I don't have too much of knowledge of FPGAs but if anyone has knowledge of this or can point me in the right direction it would be much appreciated.    --- Quote End ---    Since you are new to FPGAs ... Under no circumstance download a design to your board until you understand what pin constraints are. If you do, you can potentially damage your (expensive) board!  My recommendation would be to also buy a lower-cost DE0-nano or BeMicro-CV and use that to learn the fundamentals of FPGAs.  While you are learning about FPGAs, you can post questions to this forum to ask for clarification on questions you may have.  Your FPGA design sequence should be;  1. Understand what it takes to blink an LED  2. Understand what it takes to blink an LED using Qsys, a programmable I/O pin, and JTAG  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  3. Understand what it takes to use the Transceiver Toolkit examples  I'm writing that tutorial now ... so hassle me when you want to read it :)  Cheers, Dave

[Altera_Forum]

Thanks for the reply again Dave 

 I have a DE0-nano board also that I have been practicing with for some time. I understand the fundamentals of FPGAs and have no problem in blinking LEDs and doing other somewhat more complex stuff with VHDL or block diagrams.  Now that we have this S5-PCIe-HQ, it's a new world. :-) Our aim is to learn how to use it and eventually have it for transferring data at high rates. How to create a PCIe interface that we can understand and test , we have still not had any success. Now we wish to try and use the QSFP+ ports to read in data from one and transmit out the other. To get anything basic working right now would be an achievement. So far we can just blink the LEDs on the board.  It would be great if there was some step-by-step training for this board or FPGA that could eventually bring us up to a good level of understanding but I assume that they expect users of such boards to be already experts.  Yes, It would be great to read that tutorial :-) Thanks  Cheers, Paul

[Altera_Forum]

--- Quote Start ---   I have a DE0-nano board also that I have been practicing with for some time. I understand the fundamentals of FPGAs and have no problem in blinking LEDs and doing other somewhat more complex stuff with VHDL or block diagrams.   --- Quote End ---   Great!  Now, how about your understanding of Qsys? Do you know how to run a Modelsim simulation with an Avalon-MM master BFM?    --- Quote Start ---   Now that we have this S5-PCIe-HQ, it's a new world. :-)    --- Quote End ---   Nah, its the same world, but your mistakes just get more expensive :)    --- Quote Start ---   Our aim is to learn how to use it and eventually have it for transferring data at high rates. How to create a PCIe interface that we can understand and test , we have still not had any success. Now we wish to try and use the QSFP+ ports to read in data from one and transmit out the other. To get anything basic working right now would be an achievement. So far we can just blink the LEDs on the board.   --- Quote End ---   Did you try reading through the Transceiver Toolkit documentation?    --- Quote Start ---   It would be great if there was some step-by-step training for this board or FPGA that could eventually bring us up to a good level of understanding but I assume that they expect users of such boards to be already experts.  Yes, It would be great to read that tutorial :-)   --- Quote End ---   Yep, I figured that :)  I'll work on it next week.  For now, take a look at the notes below on what I needed to do to get a Transceiver Toolkit design working with an Arria V. I'm pretty sure there is already a Stratix V design in the toolkit examples, so all you need to do, is to ensure that the top-level pin assignments for the transceiver are switched to those used on your board.  If you use a QSFP+ loopback or a QSFP+ direct attach copper cable that does not have redriver ICs, then you do not need to talk to the I2C controller in the QSFP+ cable to enable the lanes.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I just see your reply now.   I don't know how to run a Modelsim simulation with an Avalon-MM master BFM but would like to know.  I am just about to read your notes now on the Transceiver Toolkit design and thanks for that. If I use a QSFP+ loopback, do I need to link a cable between the two ports or can do it without?  Cheers, Paul

[Altera_Forum]

Hi Paul, 

  --- Quote Start ---   I don't know how to run a Modelsim simulation with an Avalon-MM master BFM but would like to know.   --- Quote End ---   Go through this tutorial;  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  This was written for an older version of Quartus, but the same general procedure works. Its written in SystemVerilog, since at the time, the Altera Verification IP Suite did not have good VHDL support. There is better support for VHDL now, however, I haven't used it, since simulation in SystemVerilog is ok with me (even though my synthesis code is in VHDL).    --- Quote Start ---   If I use a QSFP+ loopback, do I need to link a cable between the two ports or can do it without?   --- Quote End ---   There's several loopback options;  1. A physical loopback connector that connects the TX and RX pins in the QSFP+ connector  http://www.elpeus.com/categories/qsfp-cables/qsfp-loopback-adapters.html  2. Internal loopback at the transmitter (nothing needed on the QSFP+ connector)  3. Internal loopback at the receiver (needs a QSFP+ cable between the transmitter and receiver)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I've been going through that tutorial and it helps alot.  The tutorial supplied test-bench on p.28 (Avalon-MM Master BFM) does not work however. When I try to compile using "vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L qsys_system_bfm_master" , I receive errors saying that could not find the package verbosity_pkg and avalon_mm_pkg.  The test-bench JTAG-to-Avalon-MM Master on P.29 works tho.  On p.31 under Synthesis and Simulation scripts it says to start Quartus and change to the Qsys BeMicro-SDK project and then use commands like "tcl> set TUTORIAL c:/temp/altera_jtag_to_avalon_mm_tutorial". How exactly do I do that in Quartus. Are those tcl commands?  I am having problems also understanding how to implement the host-to-FPGA communication from p.33. There doesn't seem to be a step-by-step guide on how it is done.  Thanks again for your help, Paul

[Altera_Forum]

Hi Paul, 

  --- Quote Start ---   The tutorial supplied test-bench on p.28 (Avalon-MM Master BFM) does not work however. When I try to compile using "vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv -L qsys_system_bfm_master" , I receive errors saying that could not find the package verbosity_pkg and avalon_mm_pkg.   --- Quote End ---   Yes, Altera has trouble keeping things consistent between tool versions. Take a look at the qsys_vip.zip in this thread:  http://www.alteraforum.com/forum/showthread.php?t=32952&page=3    --- Quote Start ---   On p.31 under Synthesis and Simulation scripts it says to start Quartus and change to the Qsys BeMicro-SDK project and then use commands like "tcl> set TUTORIAL c:/temp/altera_jtag_to_avalon_mm_tutorial". How exactly do I do that in Quartus. Are those tcl commands?   --- Quote End ---   Yes, those are Tcl commands. If the Quartus Tcl console is not visible, you can access it via View->Utility Windows->Tcl console.    --- Quote Start ---   I am having problems also understanding how to implement the host-to-FPGA communication from p.33. There doesn't seem to be a step-by-step guide on how it is done.   --- Quote End ---   "Its just software" :)  The step-by-step guide is to read the software, eg., the Tcl scripts.  Altera started with a tool called quartus_stp, but have moved their focus onto the System Console tool.  Download the bemicro_cv_examples.zip file from this thread (the version from post# 5)  http://www.alteraforum.com/forum/showthread.php?t=43992  and look in the ddr/scripts folder at jtag_cmds.tcl. All you really need to understand is; open/close and read/write.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 When I send the command from page 31 : "source scripts/synth.tcl" , I receive the error: "error: can't find package ::quartus:: project while executing package require ::quartus:: project"(file "scripts/synth.tcl" line 45) while executing..".  Do you know what the issue is?  Also, when I get to the point of communicating with the board from the the host, If I write a value to RAM for example, how can I confirm that the value is there? Can I also use pin planner to assign the LED ports to the pins on my DE0-Nano board and then observe them changing when I send tcl commands (after re-compiling and programming the board of course) ?   Thanks, Paul

[Altera_Forum]

--- Quote Start ---   When I send the command from page 31 : "source scripts/synth.tcl" , I receive the error: "error: can't find package ::quartus:: project while executing package require ::quartus:: project"(file "scripts/synth.tcl" line 45) while executing..".  Do you know what the issue is?   --- Quote End ---   So long as you are sourcing that script from the Quartus II Tcl console, it should work fine.     --- Quote Start ---   Also, when I get to the point of communicating with the board from the the host, If I write a value to RAM for example, how can I confirm that the value is there?   --- Quote End ---   Read it back :)    --- Quote Start ---   Can I also use pin planner to assign the LED ports to the pins on my DE0-Nano board and then observe them changing when I send tcl commands (after re-compiling and programming the board of course) ?    --- Quote End ---   Sure, if you make sure the pin planner assignments are correct for your hardware, then you can rebuild the design for your specific hardware.  Cheers, Dave

[Altera_Forum]

I have sourced the tcl file "..\hdl\boards\bemicro_sdk\share\scripts\jtag_cmds_sc.tcl" but when I then try to change the LED values with command "led write 0x23" for example, nothing happens. I assume that that tcl commands script is specifically for the bemicro board.  

If that is just the issue, where can I get one that suits the DE0-nano board? I am not a pro at tcl so unable to create my own.  Cheers, Paul

[Altera_Forum]

Hi Paul, 

   --- Quote Start ---  I have sourced the tcl file "..\hdl\boards\bemicro_sdk\share\scripts\jtag_cmds_sc.tcl" but when I then try to change the LED values with command "led write 0x23" for example, nothing happens. I assume that that tcl commands script is specifically for the bemicro board.   --- Quote End ---   This Tcl script is expected to be used from within SystemConsole ... is that where you sourced it?   So long as you did not change the PIO address in the Qsys system, this script will work with any board. The board-specific change needed is the pin assignments.  Cheers, Dave

[Altera_Forum]

Yes I have sourced the file from within SystemConsole under TCL console. I have tried to source the jtag_cmds_sc.tcl for the de2 and also bemicro but when then try to change the LEDs , I receive error : "Sorry, no master nodes found 

error: can't read "jtag(master)": no such variable" .  I am looking at the System Console interactive session in Figure 13. Must I use these commands? I am just doing what is in Figure 14 , which is sourcing the tcl file and then trying to change LEDs etc.   I also use pin planner to assign the LED ports to actual pins on the cyclone IV. Is this necessary, because I don't see this in the notes? If that is the case , must I assign all the ports there, including tck,tdi,tdo,tms?  Sorry for the bombardment of questions, but we are determined to get it right ))  Cheers, Paul

[Altera_Forum]

--- Quote Start ---  Yes I have sourced the file from within SystemConsole under TCL console. I have tried to source the jtag_cmds_sc.tcl for the de2 and also bemicro but when then try to change the LEDs , I receive error : "Sorry, no master nodes found error: can't read "jtag(master)": no such variable" .   --- Quote End ---   Use this as an opportunity to understand what the scripts do :)  1. Make sure your design contains a JTAG-to-Avalon-MM bridge.  If you look in the hierarchy display in Quartus after synthesis, you should see an sld_hub, and then if you expand the Qsys system, you'll see the jtag_master.  2. Read the SystemConsole Tcl script and read the Quartus handbook section that describes the commands.  The "Sorry, no master nodes found" comes from the jtag_open command, i.e., the Tcl commands   set master_paths if { == 0} { puts "Sorry, no master nodes found" return }   The Quartus command "get_service_paths master" returns a list of JTAG-to-Avalon-MM bridge components in your design. The fact that it does not find any means that you've either forgotten to download the board, or some other issue.    --- Quote Start ---   I am looking at the System Console interactive session in Figure 13. Must I use these commands? I am just doing what is in Figure 14 , which is sourcing the tcl file and then trying to change LEDs etc.    --- Quote End ---   If you compare Figure 13 to the jtag_cmds_sc.tcl script, you'll see that the Tcl script simply wraps those commands in user-friendly set of procedures, so what you have done is fine. The problem is that your design is not recognized as having a JTAG-to-Avalon-MM master, i.e., the jtag_open procedure called the first time you try to use jtag_read or jtag_write is failing.    --- Quote Start ---   I also use pin planner to assign the LED ports to actual pins on the cyclone IV. Is this necessary, because I don't see this in the notes? If that is the case , must I assign all the ports there, including tck,tdi,tdo,tms?   --- Quote End ---   Yeah, you're right, this could be stated a little more explicitly. To a long-time user of FPGAs, its "obvious" that pin assignments change between boards, but this is not the case for new users :)  You must assign the clock and LED pins correctly. The JTAG pins are fixed, so don't worry about assigning them.    --- Quote Start ---   Sorry for the bombardment of questions, but we are determined to get it right ))   --- Quote End ---   No need to apologize. The tools are often annoying. I've already suffered through the pain and frustration, so I don't mind saving others some grief :)  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 This would be a separate issue. I have posted it in another forum but no reply yet.   I am following the example tutorial "Using the SDRAM on Altera’s DE2 Board with Verilog Designs" using Qsys. I have built the system and loaded it to the FPGA. I am using the DE0-Nano board again.  How exactly can I test the DDR2 controller in this case? I see only an example on how to test the switches and LEDs there.  I would like to be able to write data to the on-board RAM through the controller from the FPGA and read it back etc. Do I have to worry about all the control signals or will the controller take care of that itself? In order to write data to an address in RAM, how would one go about it?  Thanks, Paul

[Altera_Forum]

Hi Paul, 

  --- Quote Start ---   This would be a separate issue. I have posted it in another forum but no reply yet.    --- Quote End ---   I guess I didn't see it :)    --- Quote Start ---   I am following the example tutorial "Using the SDRAM on Altera’s DE2 Board with Verilog Designs" using Qsys. I have built the system and loaded it to the FPGA. I am using the DE0-Nano board again.  How exactly can I test the DDR2 controller in this case? I see only an example on how to test the switches and LEDs there.   --- Quote End ---   The DE0-nano has SDRAM, not DDR2 ... so your question is inconsistent ...  With DDR memory, the controller is quite complicated and requires calibration of the interface timing. This can be performed using the Transceiver Toolkit. I'm sure your Stratix V board uses DDR2, so I can send you a document on how to create a system that includes the logic required to use the Transceiver Toolkit.  The SDRAM memory on the DE0-nano has static timing requirements. So long as the design includes the correct .sdc file, and it passes timing, then you can just use it. You can test it using a pattern generator and checker, and DMA controller to move data back and forth, or you can just create a really basic test, and read/write.    --- Quote Start ---   I would like to be able to write data to the on-board RAM through the controller from the FPGA and read it back etc. Do I have to worry about all the control signals or will the controller take care of that itself? In order to write data to an address in RAM, how would one go about it?   --- Quote End ---   The controller takes care of the timing.  You should also be able to create a simulation of the system and include a memory model and read/write that fake memory. If you get that working, then you'll feel a lot more confident things work.  I have a favor to ask ... Do you have any QSFP+ cables for your board yet? I would like to see what the eye pattern measurements are like on the Bittware board. If you have a cable, I can write the top-level HDL, and you can run the test. That way you'll get a working design, and I'll get the test results I want to see, and then I can decide whether I should get one of the Bittware boards.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 We are still waiting on the QSFP+ cables for the board. They should hopefully get here before the end of the month. As soon as they arrive I will let you know.  The DE0-nano has SDRAM actually, my bad :-) I therefore don't have an example on how to read and write to it. What would be the best way to do this?  Yes the Bittware board has DDR3 RAM. It would be great to receive a document on how to read and write to it also.   Thanks, Paul

[Altera_Forum]

Hi Paul, 

  --- Quote Start ---   We are still waiting on the QSFP+ cables for the board. They should hopefully get here before the end of the month. As soon as they arrive I will let you know.   --- Quote End ---   Ok, thanks. I could always FedEx you my cables if I was dying for the data sooner. Can you send me an email (to the email address that is my forum name) with the zip file to the Bittware board installation. I'll install it on my development machine, and that way I can create example designs for the board for you.    --- Quote Start ---   The DE0-nano has SDRAM actually, my bad :-) I therefore don't have an example on how to read and write to it. What would be the best way to do this?   --- Quote End ---   Using the JTAG-to-Avalon-MM master.    --- Quote Start ---   Yes the Bittware board has DDR3 RAM. It would be great to receive a document on how to read and write to it also.    --- Quote End ---    Download the example design for the BeMicro-CV that I posted here (post#5)  http://www.alteraforum.com/forum/showthread.php?t=43992  and it has the basic sequence. If you get stuck, and you've sent me the Bittware design files, I'll be able to help you figure it out.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 I have sent you an email also.  I have tried that JTAG-to-Avalon master tutorial but it just uses on-chip RAM. If I wish to use the separate SDRAM on the DE0-nano board, do I just add an SDRAM controller in Qsys instead of on-chip RAM?  How would I then make sure that it communicates with the SDRAM on the board. Looking at the DE0-nano user guide , there are many pins connected to the SDRAM so which pins would I need to assign and to where?  Cheers, Paul

[Altera_Forum]

--- Quote Start ---   I have sent you an email also.   --- Quote End ---   Thanks!    --- Quote Start ---   I have tried that JTAG-to-Avalon master tutorial but it just uses on-chip RAM. If I wish to use the separate SDRAM on the DE0-nano board, do I just add an SDRAM controller in Qsys instead of on-chip RAM?    --- Quote End ---   The tutorial is written to be board agnostic, so it does not use any external devices. In your case, you would simply *add* an SDRAM controller to the Qsys system, and assign it a base address that does not conflict with the existing memory map.    --- Quote Start ---   How would I then make sure that it communicates with the SDRAM on the board. Looking at the DE0-nano user guide , there are many pins connected to the SDRAM so which pins would I need to assign and to where?   --- Quote End ---   The attached zip file contains a top-level design and a constraints file that defines all the pins on the DE0-nano.  If you cannot figure out how to add an SDRAM controller to the design, I can take a look, but you should try to figure it out, as it will be a good learning experience. You should also try to figure out how to create a simulation for the system (that will likely be a little trickier though).  Cheers, Dave

[Altera_Forum]

I have added the SDRAM controller to the qsys and assigned all the pins. 

 The next step tho I have trouble with and that is how to use it. I have tried that example of writing to the RAM from the host computer via the jtag interface but would like to do it differently.   How to read and write to the SDRAM with either VHDL code or a NIOS program? Must I specify the RAM address everytime on the address lines or do I just send data on data lines? How then would I read the data at a specific SDRAM location? I have been trying to find an example of how this is done but no success yet.  Cheers, Paul