Terasic System Builder VHDL Output

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Terasic System Builder VHDL Output

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Hi,

I'm using Terasic's openVINO development board for the cyclone V. They provide a system builder utility to create the top-level design entity which is meant to prevent you from damaging the board by misassigning pins.

In the manual for the openVINO it says you can choose either .v or .vhd files. But in the actual software I can't find any option for this. Has anyone managed to generate .vhd top level entity with the Terasic System Builder or have any tips for converting the .v file to .vhd.

Thankyou,
Django

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