Transcoder's propagation time getting longer in Cyclone 5 than in Cyclone 4

[WKhad1]

Hi,

i have programmed a transcoder of 8 stages to transcode 256 bits into 8 bit. It worked perfectly on Cyclone 4 device.  

I'm trying to upgrade this project to a Cyclone 5 Kit (DE-10 Nano).

after compiling the project, firstly only the first two stages appear in the chip planner. i forced the fitter to place all the 8 stages. but the problem is that when i report the path from the input of the first stage to the output of the last stage i found that it's

 12.3 ns on the cyclone5

while it was

8.531 on the Cyclone4

i used this transcoder in a project with a high frequency (till 140 MHz) so that might cause a problem in the functionality

is it normal? is it because of the difference in the structure of the logical elements between the two KITs?

do you have any suggestion to overtake this problem

Thanks in advance

[MuhammadAr_U_Intel]

Hi, To answer your first question where few stages doesn't appear, this might be due to rest of the stages were getting optimized since output is not used, you might want to look for why are they optimized. Secondly what is the target frequency you have selected to constrain the design, you should look for static timing analysis report to find if the design can run on desired frequency, in case it failed in reports you can reduce frequency or try to optimize the design. Hope this helps. Thanks, Arslan