Transfer Data from Nios II to FPGA using Avalon-ST

[aamodini]

I am trying to transfer a chunk of data from Nios II to the FPGA fabric using the Avalon Streaming interface, and am facing a couple of challenges in implementing the same.

1. I'm unable to connect almost_full and almost_empty signals to the sink.

2. Are the driver APIs same as those available for Avalon FIFO Memory IP? If yes, how do we write data to the FIFO and read from it using Avalon-ST? I am unable to generate in_csr base address.

[sstrell]

1) Not sure why you want to connect these status signals to the sink (which sink?).  They are single bit Avalon streaming status signals that indicate when the FIFO is above or below the thresholds you've set, which is accessible via CSR access: https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/register-description-68335.html

2) This is Avalon streaming, not memory-mapped, so there would be no API.  You would control whatever component drives data into the FIFO (another source component).  I don't think NIOS has a streaming option (I could be wrong on that; and FYI you should be looking at NIOS V since NIOS II is basically discontinued at this point) so I'm not sure why you are looking at this FIFO instead of a memory-mapped FIFO.

[aamodini]

1. I see two warnings on the Platform Designer that say almost_full and almost_empty signals must be connected to an Avalon-ST sink (as seen in the first image attached). Hence I was just wondering if they should be connected.

2. Does it mean I would just write to the FIFO just as I would in the case of a simple array/buffer?

Oh I wasn't aware NIOS doesn't support streaming. Is there a documentation that says so?

Thanks for the inputs!