What would happen if VCCPD and VCCIO were delayed tens of minutes to power up after VCC was powered up already for 5CEA9 device?

[XG_Kang]

In a 5CEA9 design， first power up VCC， and then VCCPD & VCCIO in all IO banks are not powered up right now, but at sometime later in tens of minutes，what will happen to the FPGA device? Will the FPGA device be damaged ?

[AnandRaj_S_Intel]

Hi,

1. VCCPD is monitored by POR circuitry, So you have to power on it within the maximum power supply ramp time, tRAM. If tRAMP is not met, the Cyclone V device I/O pins and programming registers remain tri-stated, during which device configu‐ ration could fail.
2. VCCIO is not monitored by POR so you can powers up at any time.

Are you using same regulator for VCCPD and VCCIO ?

Please check AN662, Power Management in Cyclone V Devices & Cyclone V Devices handbook for POR requirement.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

[XG_Kang]

Thanks for your reply, Anand,

The reason that I do this is to lower the power consum​ption of the FPGA device when the FPGA is not needed to work. So I want to shut some power rail but at the same time the FPGA should keep the configuration correctly.

I will check AN662 carefully.

[XG_Kang]

VCCPD and VCCIO may be different, there are seperate regulators for VCCPD and VCCIO