Why is Quartus creating modules without valid VHDL/verilog identifiers?

[FPGAUserhr10]

I am attempting to build a project for the A10 soc development kit, and it fails and shows errors about not valid VHDL/verilog identifiers. Please see the attached screenshot.

[KhaiChein_Y_Intel]

Hi,

May I know which edition and version of the software you are using? Kindly share the testcase for investigation.

Thanks.

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY