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displayport™ 1.4 TX only example design for Cyclone10 GX

slmel
Novice
414 Views

 

Hi,

We are currently working on Display port IP in Cyclone 5 GT board and Cyclone 10 GX. We started working on Cyclone 5 GT board. In this we used bitec HSMC board. Loop back example design worked well for us. But when we connected TPG data and sync signals instead of RX signals, the design didn't work. (I have tried TX only example design from Intel wiki too. that also didn't work). Could you please help me on this 

Our custom board is based on Cyclone 10 GX. I have gone through displayport™ 1.4 video presentation series in youtube from following link.

https://youtu.be/GULMO1s15LM

 

Did I get project files of those example design?

 

Rgds,

SLM

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1 Solution
Deshi_Intel
Moderator
359 Views

Hi,


I found out below AN doc that may provide answer to you.


It's still referring to A10 DisplayPort Tx only Example Design but C10 GX DisplayPort design should be quick close to it as well

  • Pls go through the AN doc in detail to learn about DisplayPort Tx only example design
  • Chapter 1.4.4 - tell you on some debug feature
  • Chapter 1.5 - teach you how to convert DP Rx to Tx example design to become DP Tx only example design


Since you are using custom board then it's very hard to isolate whether the failure is on board issue or Quartus design issue

  • If you have Cyclone 10 Gx dev kit + Bitec DisplayPort daughter card then it will be easier to isolate out board issue


Thanks.


Regards,

dlim


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7 Replies
Deshi_Intel
Moderator
397 Views

Hi,


May I know are you trying to debug DisplayPort design issue on Cyclone V FPGA or Cyclone 10 GX FPGA ?


We do have some DP Tx only reference design that you can check out in Intel FPGA design store in below link


Thanks.


Regards,

dlim


slmel
Novice
391 Views

Hi,

We need to test it in Cyclone 10 GX. Within the link you have shared I couldn't find any Cyclone 10 example design. I have tried C5 Tx only example using Q17. But it didn't work. Could you please help on this?

 

I have created tx only system based on the video in the Intel channel. Could you please explain how to debug the DP if video will not output?

 

Also from below post I have seen that  it is required to checked "Enable Video Input Image Port" in order to build TX only system. Is it required. I couldn't find this in any of the example design mentioned in above link you have shared. Could you please clarify this point?

https://community.intel.com/t5/FPGA-Intellectual-Property/DisplayPort-TX-IP-in-image-video-mode/m-p/...

Rgds,

Slm

Deshi_Intel
Moderator
381 Views

Hi SLM,


The other forum link that you shared to me is for other user custom design debug. You can ignore it.


For your case,

  • You should not use Cyclone V design as Cyclone 10 GX and Cyclone V is having different design architecture
  • Intel doesn't has Cyclone 10 GX Tx only example design. The closest reference that you can refer to is Arria 10 Tx only example design. Arria 10 Tx only design is available in the link that I shared with you earlier.


Before you test out Cyclone 10 Gx Tx only example design,

  • Pls make sure the default Cyclone 10 Gx Rx to Tx re-transmit example design is working on your board first.
  • After that, you can then modify "Cyclone 10 Gx Rx to Tx re-transmit example design" to become "Cyclone 10 GX Tx only example design" by referring to Arria 10 Tx only example design


Thanks.


Regards,

dlim




Deshi_Intel
Moderator
381 Views

You can also refer to below C10 DP Rx to Tx Re-transmit example design user guide doc to learn more about the example design


Thanks.


slmel
Novice
374 Views

Thank you Dlim for your support. In our case Cyclone 10 Gx board is our custom board and it has only transmit side.  So we couldn't try RX-Tx loop back in the case of Cyclone 10Gx. That is why we tried Cyclone 5 board in order to get an idea how to change Rx-TX design to Tx only design.  Is it okay to take Cyclone 10 Gx loopback and modify according to Arria 10?

 

Also how we can debug this DP using signaltap or any other quartus tool?

Regds,

Slm

 

 

Deshi_Intel
Moderator
360 Views

Hi,


I found out below AN doc that may provide answer to you.


It's still referring to A10 DisplayPort Tx only Example Design but C10 GX DisplayPort design should be quick close to it as well

  • Pls go through the AN doc in detail to learn about DisplayPort Tx only example design
  • Chapter 1.4.4 - tell you on some debug feature
  • Chapter 1.5 - teach you how to convert DP Rx to Tx example design to become DP Tx only example design


Since you are using custom board then it's very hard to isolate whether the failure is on board issue or Quartus design issue

  • If you have Cyclone 10 Gx dev kit + Bitec DisplayPort daughter card then it will be easier to isolate out board issue


Thanks.


Regards,

dlim


slmel
Novice
342 Views

Hi Dlim,

 

Thank you for your reply. The document you shared helped usto debug C5 issue. Now Tx only system working in C5. In that we didnt made BITEC_EDID_800X600_AUDIO = 0. So our output always supported 800x600 resolution as maximum one! Is this parameter affect video too?

 

Hope this knowledge will help us to implement Tx only system in C10. 

 

Regards,

Slm

 

 

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