enable secure JTAG in max10 lockup board.

[NYup]

Error (209014): CONFIG DONE is FAILED to go high

What is the problem?

I am using Quartus version 18.0 on linux.

FPGA MAX10 device number 10M08SAM156CBG

I enable Secure JTAG with Intel provided Internal JTAG block

with UNLOCK/LOCK ports out to I/O.

I pulled on UNLOCK port HIGH, send in UNLOCK JTAG COMMAND

via quartus_jli

[nyup@labOptiPlex2 test_unlock]$ quartus_jli -c 2 unlock_208.jam -a unlock

Info: *******************************************************************

Info: Running Quartus Prime Jam Tools

   Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition

   Info: Copyright (C) 2018 Intel Corporation. All rights reserved.

   Info: Your use of Intel Corporation's design tools, logic functions

   Info: and other software and tools, and its AMPP partner logic

   Info: functions, and any output files from any of the foregoing

   Info: (including device programming or simulation files), and any

   Info: associated documentation or information are expressly subject

   Info: to the terms and conditions of the Intel Program License

   Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

   Info: the Intel FPGA IP License Agreement, or other applicable license

   Info: agreement, including, without limitation, that your use is for

   Info: the sole purpose of programming logic devices manufactured by

   Info: Intel and sold by Intel or its authorized distributors. Please

   Info: refer to the applicable agreement for further details.

   Info: Processing started: Fri Sep 20 14:33:36 2019

Info: Command: quartus_jli -c 2 unlock_208.jam -a unlock

Info: Using INI file /opt/intelFPGA/18.0/quartus/linux64/quartus.ini

Exit code = 0... Success

Info: Quartus Prime Jam Tools was successful. 0 errors, 0 warnings

   Info: Peak virtual memory: 194 megabytes

   Info: Processing ended: Fri Sep 20 14:33:39 2019

   Info: Elapsed time: 00:00:03

   Info: Total CPU time (on all processors): 00:00:00

-----------------------------

'Altera 2016

'Purpose: To unlock

ACTION unlock = DO_UNLOCK;

PROCEDURE DO_UNLOCK;

DRSTOP IDLE;

IRSTOP IDLE;

STATE IDLE;

IRSCAN 10, $208;

WAIT 100 USEC;

EXIT 0;

ENDPROC;

I tried with $041; too

[YuanLi_S_Intel]

Hi Nhu,

I believe this is the duplicated case of 04351475. I will continue to support your request in this case 04351475.

Thank You.

[YuanLi_S_Intel]

Hi Nhu,

This is weird. By right it should be able to program after you UNLOCK it. May i know, have you observed if "indicator" port is going HIGH? You may also refer to the steps to UNLOCK as shown at link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf (Page 58)

Thank You.

[NYup]

The indicator isn’t accessible on our system board . I will ask Bert our local FAE whose evaluation board is locked up to see what it is . Thanks Nhu-Ha

[NYup]

What does the checkbox for jtag enable do ? Does the WUSIWUG control the config_done pin? I got 3 boards locked up and bought a couple more evaluations board. But I don’t want to lock them up again . Nhu-Ha

[NYup]

Yes I did run the Lock_Unlock_complete signal to an LED indicator. It turns on, indicating complete, not sure what is complete With the light on, the programmer lets me try to send a file (either POF or SOF) but fails When the light is off the programmer detects no device and doesn’t let me set up a file to be programmed, it just assumes there is no FPGA present. I have sent the QAR file for my design to IPS, not sure what they will do with it as they need the specific HW board. Nhu-Ha Yup Rajant Corporation 4505 E. Chandler Blvd. #250 Phoenix, AZ 85048 nyup@rajant.com <cmercer@rajant.com> P: 602-362-2150 x2216

[NYup]

Nhu-Ha Yup Rajant Corporation 4505 E. Chandler Blvd. #250 Phoenix, AZ 85048 nyup@rajant.com <cmercer@rajant.com> P: 602-362-2150 x2216

[NYup]

any suggestion how to unlock the board. I have not heard anything for a long time Nhu-Ha Yup Rajant Corporation 4505 E. Chandler Blvd. #250 Phoenix, AZ 85048 nyup@rajant.com <cmercer@rajant.com> P: 602-362-2150 x2216

[YuanLi_S_Intel]

Hi Nhu-Ha Yup,

Sorry for the late, WYSIWYG is an internal JTAG interface. It doesn't control CONF_DONE pin directly but if the configuration is working successfully, the CONF_DONE pin will be asserted.

Just would like to check, have you used our reference design and also the JAM file provided? Or you use your own and obtain the following error? Please let me know.

Just for your information, you can obtain the reference design at link below:

https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/max10-jtag-secure-unlock/

The steps to use the reference design is in this AN556:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an556.pdf

Thank You.

[YuanLi_S_Intel]

Sorry the document should be referring to this instead of AN556:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf#page=53

[NYup]

It doesn’t work. I also refer to that document . My board is locked up . I can’t erase or reload anything. Please tell me how to unlock the board Nhu-Ha

[NYup]

Will you send me your QAR for your max10 evaluation board ? I can try it on my max 10 evaluation board . Please tell me how you pulse unlock command. Nhu-Ha

[NYup]

Hello, You said your board is working with secure Jtag. I asked you last week if you will send me the QAR for your max 10 board. I have not heard back from you. It will help me alot since I have been stuck for months now. Nhu-Ha Yup Rajant Corporation 4505 E. Chandler Blvd. #250 Phoenix, AZ 85048 nyup@rajant.com <cmercer@rajant.com> P: 602-362-2150 x2216

[NYup]

Any suggestions on how to unlock the board?? Nhu-Ha Yup Rajant Corporation 4505 E. Chandler Blvd. #250 Phoenix, AZ 85048 nyup@rajant.com <cmercer@rajant.com> P: 602-362-2150 x2216

[YuanLi_S_Intel]

Hi Nhu-ha,

I have just tested on my side, seems like no problem in locking and unlocking. Just would like to check, how do you unlock the MAX10? From the above statement, seems like u were running the command to unlock. If it so, can you try to provide a pulse only to UNLOCK pin? With the unlock pulse, the JTAG will be changed from internal JTAG mode to external JTAG mode and thus you can do programming and erasing using JTAG. No command is needed to unlock.

Also, speaking about the design, once you program the POF file obtained from the reference design available at link below:

https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/max10-jtag-secure-unlock/

The device will change into JTAG secure mode once the device is powered on.

Thank You.

[NYup]

We power down and the next day the board is locked up . I will ask Robert Polk our FAE to answer tell you what he did since he locked up the evaluation board w just your secure jtag design Nhu-Ha

[YuanLi_S_Intel]

Hi Nhu-Ha Yup,

Any update from FAE? For your information, just send a pulse to UNLOCK pin (Assert to HIGH then deassert to LOW), the board will unlock.

Thank You.