hi:I have make a custom component which is added into my SOPC system,the component mainly consist of a FIFO (quartusII megacore ) ,the FIFO signals are as below: FIFO this_fifo(.aclr(reset_n), .data(active_data), .rdclk(clk_50M), .rdreq(sl_read & sl_chipselect), .wrclk(clk_27M), .wrreq(start ), .q(sl_readdata), .rdusedw(rdusedw), .wrusedw(wrusedw) ); the aim of the SOPC component(avalon slave component) is to translate the a large number of digital video data to SDRAM ,in NiosII eclipse, I write a instruction to read data from the SOPC component: IORD_ALTERA_AVALON_PIO_DATA(COMPONENT_BASE),but the wave is wrong through signaltapII ,the readdata is always zero,and sl_chipselect and sl_read are zero too,the data seems cannot be read out from FIFO,and the wave does'nt conform to the standard wave of avalon slave conponent I post the hdl code and signaltap window as attarchments.please give me some hints. thanks for your replay, I am very urge for the task!!~
The macro you are using is for the PIO component. You want to do something this instead:# include "io.h"# include "system.h" ..... read_data = IORD_32DIRECT(BASE_ADDRESS_OF_SLAVE, BYTE_OFFSET); "BASE_ADDRESS_OF_SLAVE" is whatever your custom component shows up as in system.h and "BYTE_OFFSET" is the offset inside your component you are reading from, make sure you express the offset in bytes and not 32-bit words. Looking at your HDL I see a couple of issues: 1) You have 18 bits of addressing but no address decoding, so a read from any address will pop the FIFO 2) You don't prevent reads from the FIFO when it's empty. Waitrequest should be driven high when the FIFO is empty and the rdreq of the FIFO should be gated by this condition. 3) You are driving the FIFO aclr with an active low reset_n signal, in other words your FIFO is stuck in reset and that's why no data is moving through
hi:thanks for your reply!~ I have added the .h files in niosii software,and I writed : IORD_ALTERA_AVALON_PIO_DATA(BASE_ADDRESS_OF_SLAVE); fogive me making some writing mistakes!~~ Coulde I ask you a quesion: !: the data writen into FIFO ,how to make sure their address in SOPC memory map?the system,h only can tell us the SOPC component base address.so I donnot know how to use slave_address,and let if point to FIFO data's address(I am sorry that building custom SOPC conponent is still somekind hard for me~) best regards~
Any slave port connected to the Nios II instruction or data master will appear in the system.h file generated in your system library or BSP. The base address defined will be based on the name that you instantiated the component as in SOPC Builder. So if you called your component in your system "my_fifo" then you could expect to fine something like this in the system.h file:# define MY_FIFO_BASE <some base address> If you component is only a FIFO then you really only need a single address location to read from. If you have multiple values besides the data inside the FIFO to read back then you build up address decoding (optionally) and typically include a multiplexer driven by the address line. For example if I created a FIFO that I can read data from and also read the 'used' signal I would do something like this: assign pop_fifo = (slave_read == 1) & (fifo_empty == 0); // should only read from FIFO when it's not empty assign waitrequest = (fifo_empty == 1); // read request should not complete until there is data in the FIFO assign slave_readdata = (address == 1'b0)? fifo_readdata : fifo_used; // reading from address 0 pops the fifo, otherwise read the used signal.
hi,BadOmenI have post another thread,name is the same as "how to read data from FIFO in SOPC", there are there questions maybe you can give me a favor. thanks