When I used Quartus to compile for a cyclone V device I got an warning, which was just the one in the link below. I followed the Workaround/Fix part of the link to try to remove the warning but failed:
There are some information about the PLL for the project:
My questions are:
First of all, there are different compensation modes in Altera PLL IP core, so it's strange that you didn't see them. You can read about them here : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf - Operation modes.
You can choose them from the GUI - you already made a selection (normal).
About your questions -
Hope that helps.
Thank you for your time.
I did choose "normal" when I generated PLL and I thought Quartus should know the way to compensate, however, I still got a warning as below:
Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks.
Then I assumed that there might be some extra options for compensation which I missed. That's why I said "When I generated PLL I didn't see the options for compensation".
Thank you and I tried it too but failed.
I'm not sure if you can see the message I replied GNg.
Yes, you are right that I could ignore it. I just have interest on why the warning is there that I may have something that can be improved.
I don't know whether it matters that I couldn't edit the PLL IP in the project.
It was also strange that I generated the PLL in Quartus Lite 18.1 and tried editing it in Quartus Lite 18.1 too, which was also met by some other people .
I might try to generate it again if no better choice.
I can see the message of GNg, and first of all, please try to do what he suggests - you need to find from netlist "~outclk_wire".
As about problems with editing of PLL in 18.1 Quartus it is another problem, you can explain the problem in more details.
Thank you for your reply.
As Even I chose "Normal mode" when generated the PLL, I still got a warning as below:
Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
Then I also tried adding a command in qsf by using assignment editor.
I tried two commands separately which could have a green tick in assignment editor as below (my PLL didn't have outclk_wire, which was generated by Quartus Lite 18.1 for cyclone V):
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general.gpll"
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general.gpll~FRACTIONAL_PLL"
The first one was generated by choosing a node in assignment editor.
The second one was copied and pasted into the assignment editor from the info that in Warning (177007).
However, I got another warning for this command:
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
So, this command didn't work, though I thought the clock output was correct.