MMIO bar doesn't work

[B-OatPQURE]

The PCI MMIO register access doesn't work as follows.

I used the following data for testing.

INDEX = 0x1000    (PCI MMIO index register)

DATA  = 0x1004     (PCI MMIO data register)

REG    = 0x1f0410 (0x180000 + 0x70410 (SWF00 register)

TEST  = 0xdeadbeef (suitable value for a failed test)

out INDEX,REG

in VALUE,INDEX (VALUE=REG, register can be read and written)

out DATA,TEST

in VALUE,DATA (VALUE=0xffffffff, register can't be written)

mov [REG],TEST

mov VALUE,[REG]  (VALUE=TEST, register can be read and written)

So the DATA portion of the PCI MMIO index,data pair is blocked and there is no documentation telling how to unblock it. So in my eyes this is an errata, as according to documentation the PCI MMIO should work.

As VBIOS use this mechanism for access to MMIO and GTT table, the unblocking must be done from system BIOS. As I have an SNDA and are a BIOS vendor, it shouldn't be a problem to get the proper documentation. I have seen that Intel often leaves out crucial information like this, so I hope that it's not intentionally.

Best regards,

B-O Bergman

PQURE Technology 

[Jocelyn_Intel]

Hello, @B-OatPQURE  

Thank you for posting on the Intel® communities.  

To assist you properly, what is the model of your graphics? 

Also, how is this issue related to graphics? Is it affecting your graphics performance?  

What are you trying to do? 

Please provide more details to understand the problem. 

Best regards,  

Jocelyn M.   

Intel Customer Support Technician. 

[B-OatPQURE]

The model of the graphics is Atom x5/x7 (Braswell/CherryView/CherryTrail). The issue relation to graphics is that configuration for text and graphics mode needs to operate on special registers that should be available by indirect access to a PCI index/data combination or directly accessed from 32-bit/64-bit mode.

The problem is that the indirect access doesn't work and it's crucial for X86 real mode operation. Real mode X86 operation is used by VGA BIOS and even boot loaders may use it for early initialisation of graphics output ports. 

According to documentation the PCI I/O registers for indirect access works like this. You write the offset of the MMIO register (display engine and GTT table) to the index register, then you either write to the MMIO register by writing to the data register or read the content of the MMIO register by reading from the data register.

Writes to the index register work and you can read back the MMIO offset from the index register. Read or writes to the data register doesn't reach the MMIO register. So writes to the data register do not change the MMIO register. Reads from the data registers always returns 0xffffffff.

The data register in the PCI I/O bar is not present. So it's blocked by something, probably connected to secure boot. The PCI bus mechanism is absolutely required for VGA BIOS operation. The system BIOS must have a mechanism for enabling or disabling the indirect access of graphics MMIO registers as a VBIOS exist for the architecture. I need to know this mechanism in order to interact with the graphics in X86 real mode.   

[Jocelyn_Intel]

Hello, @B-OatPQURE

Thank you for the information provided.  

Due to this product (Intel® HD graphics) being discontinued, Intel Customer Service no longer supports inquiries for it, but perhaps fellow community members have the knowledge to jump in and help. You may also find the Discontinued Products website helpful to address your request.   

Thank you for understanding.  

Best regards, 

Jocelyn M.  

Intel Customer Support Technician. 

[B-OatPQURE]

Hi, problem is solved. The problem was that the display engine needed to be powered on. I share this in case someone else have the same problem.

The power is witch on by clearing the PUNIT DSPSSPM register bits 0-1.

Best regards,

B-O

[B-OatPQURE · Accepted solution]

Hi, problem is solved. The problem was that the display engine needed to be powered on. I share this in case someone else have the same problem.

The power is switched on by clearing the PUNIT DSPSSPM register bits 0-1.

Best regards,

B-O