Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi,

Do you still see the error below? If yes, can you provide the design.qar for investigation?

 

Error (12006): Node instance "U0" instantiates undefined entity "BRAM_16x1S"

Error (12006): Node instance "U1" instantiates undefined entity "BRAM_16x1S"

 

For the new question on simulation: It apparently doesn't automatically use the simulation testfile that was made for a 4 to 1 Mux and its already in the VHDL file put in In- and output declarations and the to simulate input data. can you open a new forum post to make sure that there is only one question in one post? This helps to reduce confusion to the other users who have the same error and helps them to find the solution to each of the error/question easily.

 

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Sadly even saving the QAR file of the BRAM16x2 example failed to complete successfully. Therefore I also included the errorlog files into a combined rar file. Hereby added. And I will try to open the Quartus II simulation question into the correct Forum links later on.

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi,

 

The rar file is corrupted. Could you reattach?

 Capture.PNG

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, I tried to login on the Intel page to answer but the URL somehow was rejected. See attached screencopy. Therefore I answer you by using my mail for replying. (I used my Opera browser when that error page generated). I tested my supposed 'corrupted' attachment file and was completely able to open and extract all single files. So I think it is the by the Quartus II program generated files that make them unusable? Because as said I got an error warning that said the program couldn't completely generate the files because the BRAM16x1S/16x2 VHDL file wasn't entirely successfully compiled. (Note that Xilinx ISE 14.6 had no problem with this same VHDL file!). I can resend you the files again but I think that it will make no difference when Quartus fails to completely compile again? Thanks. Albert.
0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

Can you send the entire project directory in ZIP?

 

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hereby I hope to attach the right information you asked KhaiY. I attach 2 packed files. The file output files is from that Altera 13.1 map.

 

Thanks.

Hope they shed a light on solving this BRAM 16x2 question.

Albert.

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

I notice it only attached the one file upload so I try to upload the Output files file again.

 

Thanks!

Albert.

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

In the .map.rpt file you have attached, there are two error messages:

 

Error (12006): Node instance "U0" instantiates undefined entity "BRAM_16x1S" File: J:/altera/13.1/bram_16x2.vhd Line: 46

Error (12006): Node instance "U1" instantiates undefined entity "BRAM_16x1S" File: J:/altera/13.1/bram_16x2.vhd Line: 49

 

The error indicates that the BRAM_16x1S HDL file is not added to the Project. I compile the qar file, there is no BRAM_16x1S file in the project directory. Can you check if you have add this file to the project? You may check from the Project Navigator.

 

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, the vhdl file contains a component named BRAM_16x1S as part of the archive BRAM16x2 archtecture. It works splendidly as it is in Xilinx ISE 14.6. But Quartus 13.x fails to compile this same vhdl file. This is that file:

 

----------------------------------------------------------------------------------

-- Company: 

-- Engineer: 

-- 

-- Create Date:  22:57:22 05/09/2020 

-- Design Name: 

-- Module Name:  BRAM_16x2 - Behavioral 

-- Project Name: 

-- Target Devices: 

-- Tool versions: 

-- Description: 

--

-- Dependencies: 

--

-- Revision: 

-- Revision 0.01 - File Created

-- Additional Comments: 

--

----------------------------------------------------------------------------------

--BRAM_16x2 blz.194

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity BRAM_16x2 is

 

   port (q_out : out std_logic_vector (1 downto 0);

write_en : in std_logic;

clk: in std_logic;

d_in: in std_logic_vector (1 downto 0); 

a_in: in std_logic_vector (3 downto 0));

end BRAM_16x2;

 

architecture BRAM_arch of BRAM_16x2 is

component BRAM_16x1S is

port(O : out std_logic;

D: in std_logic;

A3, A2, A1, A0: in std_logic;

WE, W_CLK: in std_logic); 

end component;

 

begin

 

U0: BRAM_16x1S port map (O =>q_out(0), WE =>write_en, W_CLK =>clk, D =>d_in(0),

A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));

 

U1: BRAM_16x1S port map (O =>q_out(1), WE => write_en, W_CLK => clk, D =>d_in(1),

A0 =>a_in(0), A1 =>a_in(1), A2 =>a_in(2), A3 =>a_in(3));

 

end BRAM_arch;

-------------------------------

 

I'll add it hereby as attachement too.

 

Thanks again for taking the time to look into the problem!

Albert.

 

 

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

The BRAM_16x2vhd is instantiating the BRAM_16x1S but there is no BRAM_16x1S HDL file in the archive.

 Capture.PNG

Could you provide BRAM_16x1S ?

 

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, that is the problem, why it probably isn't working in Quartus II. But this file as it is, works splendidly in Xilinx ISE 14.6 without any problem! That is why I asked this question. I just noticed that it only works in Xilinx ISE 14.6 when a higher type FPGA is chosen. Earlier Xilinx FPGA's probably were unable to work as BRAM configurated FPGA's.

Because a Xilinx Spartan 3E failed to compile this BRAM file that works splendidly on a Xilinx Zynq XA 7z010 FPGA as it was given in the above mentioned BRAM_16x2 vhdl file from the book : PLD BASED DESIGN WITH VHDL by Vaibbhav Taraate.

 

I know too little yet about the Quartus II and Xilinx ISE programs to know why the file creates problems in Quartus II. But I guess it has to do with what version of program is used.

 

Thanks!

Albert.

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

I appreciate your explanation on the issue, but unfortunately we are not in liberty to discuss on our FPGA software especially in comparison to our competitor products.

 

I am happy to address the implementation challenges that is related to our FPGA software. In general, all the source files need to be added to the project directory for successful compilation. In this case, the software reports that the source file for BRAM_16x1S is missing in the project directory. You have to add the source file for this BRAM_16x1S if you want to instantiate it in the bram_16x2.vhd file.

 

Thanks.

Best regards,

KhaiY

 

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Understood KhaiY. But since the current file worked in Xilinx without the BRAM_16x1S file, it wasn't needed and therefore not given in the mentioned book. And if I had that file I wouldn't know how to add it to the project anyhow. Especially if it can't be added to the existing vhdl file. I already tried to do that previously to get it compiled in Quartus until I found out that it already worked in its present version in Xilinx ISE 14.6.

 

Thanks.

Best regards.

Albert.

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

In the Intel Quartus Prime software, you have to add the logic design files that contain the logic that implements your design into the Project. The source file can be in HDL(.v/.vhd/.sv), Verilog Quartus Mapping (.vqm) design files and Platform Designer (Standard) system (.qsys). It this case, it is not possible to instantiate BRAM_16x1S without the source file that describes how BRAM_16x1S works in the design.

 

To add the files into the Project

1) Click on Project > Add/Remove Files in Project

Capture.PNG

2) Click on ... icon  to add the files

Capture2.PNG

 

3) Ok

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Thanks KhaiY, I will try your much appreciated explanation later on today when I'm back from my job. I hope that I will manage to get the BRAM file running in Quartus this time.

 

Have a great day!

Albert.

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

Sure. Do let me know if you have any questions.

Thanks.

Best regards,

KhaiY

0 Kudos
Highlighted
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi Albert,

 

Do you have any other questions? If no, I shall transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Best regards,

KhaiY

0 Kudos
Highlighted
Beginner
2 Views

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).

Hi KhaiY, I haven't any other questions at the moment and haven't tried yet to write the BRAM simulator vhdl code you suggested me to add to the in Quartus II failing compilation. I am just starting to write my first simulation code if I find time and when I exactly know how to do that. Been busy with other things in electronics I know more about. Also still waiting on another book on VHDL. But Covid-19 has put shipment at a halt for the last 3 months and it seems that it isn't coming soon either from Bookvistas in India and ordered through Amazon.de. Thanks KhaiY, Best regards and thanks for you trying me to understand how some things in Quartus work. But without online connection the Quartus Help database is sadly greatly missed and should be integrated in the program for offline access. Have a great week! Albert.
0 Kudos
Highlighted
1 View

Re: I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in th

Hi Albert,


Sure. You are welcome to open a new forum thread if you need help in the future.

 

Thanks.

Best regards,

KhaiY

0 Kudos