OpenCL kernel for a DE10-standard board via OpenCL SDK 18.0.0.614 Windows 7: no top.sof file

[amara5]

I am trying to compile OpenCL kernel for a DE10-standard board via OpenCL SDK 18.0.0.614 Windows 7 using the command:

C:\intelFPGA\18.0\hld\board\de10_standard\test\hello_world\device>aoc hello_world.cl -o bin\hello_world.aocx -board=de10_standard_sharedonly -v -report

It outputs as in the attachment.

Apparently it cannot find a top.sof file

[amara5]

Does the Quartus 30 days trial license allow to compile OpenCL project?

[MuhammadAr_U_Intel]

Hi, top.sof is generated during OpenCL compilation, can you check the "bin/hello_world/quartus_sh.log" to see where did the compilation stopped ? You may want to check the requirements specified by Terasic in user guide. https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1081&PartNo=4 "DE10-Standard OpenCL User Manual" Thanks, Arslan

[amara5]

Hi Arslan,

thanks for your reply.

Please find the log file attached.

I followed the instructions contained in "DE10-Standard OpenCL User Manual".

As I wrote, my concern is about the Quartus license. On page 13 of the document, paragraph 2.2 License Installation, it is written:

"An Quartus license is required to compile OpenCL project. Users can purchase the license from

Intel. A file named “license.dat” will be given upon purchasing Quartus license."

I am afraid this could be the issue.

I am using a low cost entry level FPGA board and would like to evaluate OpenCL programming.

Thanks,

Alex

[MuhammadAr_U_Intel]

Hi ALex,

You definitely need a Quartus License to compile.

With OpenCL version 16.0 you will need License for both OpenCL and Quartus.

However with Quartus version 18.0 you only need Quartus License.

Thanks,

Arslan

[MuhammadAr_U_Intel]

I don't think it is due to the License issue. With latest compiler you don't need a separate License for OpenCL. Ref: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf PAge2. Also linking back your other thread here https://forums.intel.com/s/question/0D50P00004EtU2L/opencl-kernel-compilation-for-a-de10standard-board-via-opencl-sdk-1800614-windows-7?fromCase=1 Thanks, Arslan

[HRZ]

A Quartus license is definitely required for compiling OpenCL kernels but this problem does not seem to be related to license. I see a lot of unnatural warning in the log:

Warning (332174): Ignored filter at top.sdc(22): altera_reserved_tck could not be matched with a port or pin or register or keeper or net or combinational node or node File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 22 Warning (332049): Ignored create_clock at top.sdc(22): Argument <targets> is not an object ID File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 22 Info (332050): create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck} File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 22 Warning (332174): Ignored filter at top.sdc(23): altera_reserved_tdi could not be matched with a port File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 23 Warning (332174): Ignored filter at top.sdc(23): altera_reserved_tck could not be matched with a clock File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 23 Warning (332049): Ignored set_input_delay at top.sdc(23): Argument <targets> is an empty collection File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 23 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi] File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 23 Warning (332049): Ignored set_input_delay at top.sdc(23): Argument -clock is not an object ID File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 23 Warning (332174): Ignored filter at top.sdc(24): altera_reserved_tms could not be matched with a port File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 24 Warning (332049): Ignored set_input_delay at top.sdc(24): Argument <targets> is an empty collection File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 24 Info (332050): set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms] File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 24 Warning (332049): Ignored set_input_delay at top.sdc(24): Argument -clock is not an object ID File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 24 Warning (332174): Ignored filter at top.sdc(25): altera_reserved_tdo could not be matched with a port File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 25 Warning (332049): Ignored set_output_delay at top.sdc(25): Argument <targets> is an empty collection File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 25 Info (332050): set_output_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdo] File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 25 Warning (332049): Ignored set_output_delay at top.sdc(25): Argument -clock is not an object ID File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 25 Warning (332174): Ignored filter at top.sdc(31): fpga_button_pio[0] could not be matched with a port File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 31 Warning (332049): Ignored set_false_path at top.sdc(31): Argument <from> is an empty collection File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 31 Info (332050): set_false_path -from [get_ports {fpga_button_pio[0]}] -to * File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 31 Warning (332174): Ignored filter at top.sdc(32): fpga_button_pio[1] could not be matched with a port File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 32 Warning (332049): Ignored set_false_path at top.sdc(32): Argument <from> is an empty collection File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 32 Info (332050): set_false_path -from [get_ports {fpga_button_pio[1]}] -to * File: C:/intelFPGA/18.0/hld/board/terasic/de10_standard/test/hello_world/bin/hello_world/top.sdc Line: 32

I think the problem is likely related to a bad BSP or a bad BSP installation. I would have recommended to try Terasic's older v16.0 BSP but then you are going to have use Quartus and AOC v16.0 and AOC v16.0 requires a separate license on top of the Quartus license.

[amara5]

In the quartus_sh_compile.log I attached, line 4138:

Warning (292011): Can't generate programming files because you are currently using the Quartus Prime software in Evaluation Mode.

thanks

[HRZ]

Oh, I must have missed that one. The problem is certainly the license, then. It is probably best to contact Terasic and negotiate with them about obtaining a Quartus license.