Aktera ModelSim Lite GateLevel Simulation isn't timing accurate.

[BrianHG]

Hello,   (I'm using QuartusPrime 20.1)

I've made a simple project written in systemverilog, with a test bench file, which I compile and then do a GateLevel Simulation.

The simulation works fine, however, the gate level response it not timing accurate.

If I were to use the old fashioned 'Vector Waveform' editor, enter a clock and run a Timing simulation, this simulation is timing accurate.  The only difference I could find is that inside the folder simulation/qsim, the 'HDMI_Encoder.sft' file says:

set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
{{"Slow -7 1.2V 85 Model"} {HDMI_Encoder_7_1200mv_85c_slow.vo HDMI_Encoder_7_1200mv_85c_v_slow.sdo}}
{{"Slow -7 1.2V 0 Model"} {HDMI_Encoder_7_1200mv_0c_slow.vo HDMI_Encoder_7_1200mv_0c_v_slow.sdo}}
{{"Fast -M 1.2V 0 Model"} {HDMI_Encoder_min_1200mv_0c_fast.vo HDMI_Encoder_min_1200mv_0c_v_fast.sdo}}
}

And the ****.sdo files are generated there.

However, in the simulation/modelsim folder, the 'HDMI_Encoder.sft' file has only this 1 line:

set tool_name "ModelSim-Altera (SystemVerilog)"

And there are no '****.sdo' files being generated.

Worse, I have a project from a week ago which when I do a modelsim GateLevel Simulation. the first thing that happens is a message box pops up asking me which '****.sdo' timing model to use, and after that, modelsim does a timing accurate gate model simulation.

I do not know why the older project is generating the .sdo files and doing a proper timing simulation.  I cannot fine any difference in the 2 project settings other than the new one has a proper ***_tb.sv file which sets up the simulation stimuli.

Is there something I'm missing?

Is there a hidden Timing gate level sim VS a functional gate level sim somewhere in the start compile or start EDA netlist writer?

[RichardTanSY_Intel · Accepted solution]

Could you try below flow:

In the Quartus tool, go to : Assignment -> Settings -> EDA Tools Simulation -> Simulation -> More EDA Netlist Writer Settings -> generate functional simulation netlist -> turn it to off.

Then try to compile again to see if the .sdo file generated. 

As you may notice in the netlist setting, there is note saying : If the device does not support timing simulation, then only the functional-simulation netlist is available. 

Fyi, Timing simulation is not supported for Arria V, Cyclone V, Stratix V, and newer families. If your device does not support timing simulation, use Timing Analyzer static timing analysis rather than gate-level timing simulation. 

[BrianHG]

Thank you, that 'generate functional simulation netlist' button is well hidden.
Yes, I'm annoyed about loosing both timing simulation and the fact that the newer families during timing analysis only reports 1 last worst path instead of a good 100 of them since that 1 single worst path may be due to the fitter working around more troublesome logic elsewhere in the design.

[RichardTanSY_Intel]

You may checkout "Generate Timing Report" in the Timing Analyzer User Guide on how to customize specific timing report. 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-timing-analyzer.pdf#page=30

If you have no further question, I will transition this thread to community support. And if you have a new question, feel free to open a new thread to get the support from Intel experts.