Clarification of documentation for HPS TIMER polling operation

[KMcis]

We are using the DE10 board in our microcontroller design class. I have assigned the students a lab to use the HPS TIMER in the polling configuration.

According to the documentation (DE10-Standard_Computer_ARM Section 2.4.2 and 3.2), the M and E bits (bits 0 and 1) in the control register (Base+8) should be set to enable the repetitive counting operation with automatic reloading of the load register (Base). The documentation says:

The timer counts down to 0, and then sets both bit F in the End-of-interrupt register and bit S in the Interrupt status register to 1. Software can poll the value of S to determine when the timer period has expired. The S bit, and the F bit can be reset to 0 by reading the contents of the End-of-Interrupt register. Also, if bit I , the interrupt mask bit, in the Control register is set to 0, then an interrupt can be generated when the timer reaches 0 (note that bit I in the ARM A9 private timer shown in Figure 3 has the opposite polarity)

The implication is that bit S (0) of the status register (base+4) and bit F (0) of the end-of-interrupt register (base+3) come on when the timer reaches zero, regardless of state of bit I of the control register. The purpose of bit I is to cause (I=0) or not cause (I=1) the IRQ event when S&F come on.

However, in repeated experiments, with both Timer0 and Timer1, I find that the F and S bits do NOT come on EVER if bit I is set to 1.

I believe the HPS timer is part of the ARM HPS IP, so I can't look at the HDL to see if I'm right. I would like to give my students a clear interpretation of this passage.

Can someone confirm or deny my findings?

[Ahmed_H_Intel1]

Hi, The DE10 board is a Terasic's board and they have created all the related documents for DE10 , I apologize for not being able to answer your question, please contact Terasic for any concerns or questions about document related issue. Regards

[KMcis]

Terasic designed the board and wrote the document, but the HPS timer is Intel FPGA IP. The Cyclone V user manual contains the same information, that the I bit masks the interrupt. It doesn't say it also prevents the status bit from coming on. apparently this unit is based on the Synopsys DW_apb_timer object, but documentation for that unit seems to require membership in Synopsys. Is there no functional description that can clarify what it actually does with the I bit?

[Ahmed_H_Intel1]

Hi Ken, I will check for this and will let you know.