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Hi
I am trying to make a design using the video_sync_generator component on a de2-70 board, but i am getting strange results. For testing purposes,i connected the tree color component(Red,Green and Blue) to Vcc,so i expected to get a nice white screen but the screen is all black.The synchronization signals (VS and HS ) seem ok (the screen correctly detect the resolution). I joint a picture of my connection , if anyone have an idea or ran onto the same problem ThanksLink Copied
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Hi.
Don´t connect the R,G,B to Vcc, instead assign a value to them, while the scan time is the correct. Speaking about H signal, it is after H blanking, and before the next H blank pulse. Regards. Alberto.- Mark as New
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If you'd like a very simple example of video sync generation take a look at
http://repo.or.cz/w/yari.git?a=blob;f=rtl/target/de2-70/video.v;h=ea843e589cae2a047d56537b656d704c31e68597;hb=head This is a complete video interface for the DE2-70 minus the memory controller. This is part of YARI (http://thorn.ws/yari) I don't think the sync generation could be implemented much simpler. Tommy- Mark as New
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--- Quote Start --- Hi. Don´t connect the R,G,B to Vcc, instead assign a value to them, while the scan time is the correct. Speaking about H signal, it is after H blanking, and before the next H blank pulse. Regards. Alberto. --- Quote End --- Hi i am not sure to follow the "assign a value while the scan time is correct" part .My design is not using any .verilog (or vhdl ) file , all is done in a schematic file. Still for investigating , i modify the video_sync_generator.v file and redirect the output.Instead of having the output RGB_OUT connected to the data_input, , i directly assigned a constant to the output signal but i still get a black screen instead of a white screen Thanks
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Hi.
Why not to add an inverter between the oVGA_BLANK_N and the RGB data, and then open them from Vcc. Or did you tried leaving the 9th bit of RGB data to GND instead VCC. or did you tried with only one colour ?
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