Why not leave it as a Verilog Module and just instantiate it from your VHDL code. You can get Quartus to create the instantiate file for you and pass parameters to it if you need to alter the default settings. If the module code is OK you can just forget about it and work on your own stuff.
That depends on whether:your simulator is licensed to simulate two languages you're happy supporting a design in two languages, one of which you're not familiar you're happy that the design is actually doing what you think it is - if you can't simulate this then you might feel so certain. You always have to weigh up the risks with these things - do the advantages of translating the code outweigh the risk of introducing a bug? There is no general answer to this question - each designer has to assess it for their design.
Another option is that you might be able to place and route just this file in Quartus, with the option of producing a gate level VHDL netlist. This will give you effectively a behavioural VHDL model which you can use for simulation; the verilog rtl model you still use for synthesis.