Hi, there, I'm working on Altera's VHDL Lab Exercises, Lab7 Part1. I can not find any module named altsyncram in LMP. Can anyone suggest to me what to do?
"Implementation of UART and Timer Circuits" then you don't use the altsyncram device for RAM. The only RAM needed is onchip memory allocated in the SOPC builder.
That's not true. altsyncram can be a dual-port RAM if you want it to be, but it can also be a single-port RAM. And it's not the question that was asked.
