Intel® FPGA University Program
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I attached the code for array of pipeline d flipflop please give suggestions to rectify the synthesis error in the code .

LP5
Beginner
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Vicky1
Employee
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Hi Latha,

Here Net out[2],out[1],out[0] are driving by more than one source & that too direct wiring and that is not recommended, refer the RTL viewer.

If you want to do so you need to write priority logic for corresponding node(like multiplexer).

pipeline.JPG

 

Regards,

Vikas

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