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Hi there!
I am looking for some help or hints with Lab3 part V. I've done all the previous exercise, but I can't get any grip on that one. I've written a module which is convert a for bit binary to one digit hex. But I don't know which previous circuit should I use? A gated D latch or a RS latch or something else? Any help or a circuit schematic would be very helpfull. Cheers!Link Copied
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could be a lot more helpful if you could post your laboratory question :)
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module _7_seg(S, H);
input S;
output H;
assign H = (~S&~S&~S&S) | (~S&S&~S&~S) | (S&~S&S&S) | (S&S&~S&S);
assign H = (~S&S&~S&S) | (~S&S&S&~S) | (S&~S&S&S) | (S&S&~S&~S) | (S&S&S&~S) | (S&S&S&S);
assign H = (~S&~S&S&~S) | (S&S&~S&~S) | (S&S&S&~S) | (S&S&S&S);
assign H = (~S&~S&~S&S) | (~S&S&~S&~S) | (~S&S&S&S) | (S&~S&S&~S) | (S&S&S&S);
assign H = (~S&~S&~S&S) | (~S&~S&S&S) | (~S&S&~S&~S) | (~S&S&~S&S) | (~S&S&S&S) | (S&~S&~S&S);
assign H = (~S&~S&~S&S) | (~S&~S&S&~S) | (~S&~S&S&S) | (~S&S&S&S) | (S&S&~S&S);
assign H = (~S&~S&~S&~S) | (~S&~S&~S&S) | (~S&S&S&S) | (S&S&~S&~S);
endmodule
It converts a 4 bit binary into a single digit hexa, which can be displayed on the 7 seg display. I guess I should use 16 inscances of a gated d latch, somethig like this:
module gated_D_latch(Clk, D, Q);
input Clk, D;
output Q;
wire S, R, R_g, S_g, Qa, Qb /* synthesis keep */ ;
assign S = D;
assign R = ~D;
assign S_g = ~(S & Clk);
assign R_g = ~(Clk & R);
assign Qa = ~(S_g & Qb);
assign Qb = ~(Qa & R_g);
assign Q = Qa;
endmodule
All instances using the same Clk. But I don't know how should I wire this components up?
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if you have a 16 bit register as the input
reg input_data;
reg a,b,c,d;
you can access 4bit segments of it like
a=input_data;
b=input_data;
c=input_data;
d=input_data;
a register itself is a latch. what were you planning to achieve using the gated d latch?
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--- Quote Start --- what were you planning to achieve using the gated d latch? --- Quote End --- A circuit that can store a 16 binary number. Something like this: img132.imageshack.us/img132/7247/circx.png But instead of 4 instances I would use 16 so I could store 16 bits. ~CLR would be KEY0 CLK would be ~KEY1
module D_latch_async_rst(RST, CLK, DAT, Q);
input RST, CLK, DAT;
output reg Q;
always @ (RST or CLK or DAT)
if(~RST)
Q = 1'b0;
else if (CLK)
Q = DAT;
endmodule
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that should work.. i hope you realized that your circuit is level triggered and not edge triggered.. a 16 bit edge triggered d flip flop would look like this
module D_latch_async_rst(RST, CLK, DAT, Q);
input RST, CLK;
input DAT;
output reg Q;
always @ (posedge CLK) begin
if(~RST)
Q = 1'b0;
else
Q = DAT;
end
endmodule
i hope someone will correct me if im wrong

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