Intel® FPGA University Program
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## Laboratory exercise 3: Part V [Verilog]

Honored Contributor II
2,306 Views

Hi there!

I am looking for some help or hints with Lab3 part V. I've done all the previous exercise, but I can't get any grip on that one.

I've written a module which is convert a for bit binary to one digit hex. But I don't know which previous circuit should I use? A gated D latch or a RS latch or something else?

Any help or a circuit schematic would be very helpfull.

Cheers!
5 Replies
Honored Contributor II
564 Views

could be a lot more helpful if you could post your laboratory question :)

Honored Contributor II
564 Views

--- Quote Start ---

could be a lot more helpful if you could post your laboratory question :)

--- Quote End ---

That is obvious. Sorry. So here's the instructions from Lab3 Part V:

--- Quote Start ---

Part V

We wish to display the hexadecimal value of a 16-bit number A on the four 7-segment displays, HEX7-4. We

also wish to display the hex value of a 16-bit number B on the four 7-segment displays, HEX3-0. The values

of A and B are inputs to the circuit which are provided by means of switches SW15-0. This is to be done by first

setting the switches to the value of A and then setting the switches to the value of B; therefore, the value of A

must be stored in the circuit.

1. Create a new Quartus II project which will be used to implement the desired circuit on the Altera DE2-series

board.

2. Write a Verilog file that provides the necessary functionality. Use KEY0 as an active-low asynchronous

reset, and use KEY1 as a clock input.

3. Include the Verilog file in your project and compile the circuit.

4. Assign the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User

Manual for the DE2-series board.

6. Test the functionality of your design by toggling the switches and observing the output displays.

--- Quote End ---

This is the module that I mentioned above:

``` module _7_seg(S, H); input S; output H; assign H = (~S&~S&~S&S) | (~S&S&~S&~S) | (S&~S&S&S) | (S&S&~S&S); assign H = (~S&S&~S&S) | (~S&S&S&~S) | (S&~S&S&S) | (S&S&~S&~S) | (S&S&S&~S) | (S&S&S&S); assign H = (~S&~S&S&~S) | (S&S&~S&~S) | (S&S&S&~S) | (S&S&S&S); assign H = (~S&~S&~S&S) | (~S&S&~S&~S) | (~S&S&S&S) | (S&~S&S&~S) | (S&S&S&S); assign H = (~S&~S&~S&S) | (~S&~S&S&S) | (~S&S&~S&~S) | (~S&S&~S&S) | (~S&S&S&S) | (S&~S&~S&S); assign H = (~S&~S&~S&S) | (~S&~S&S&~S) | (~S&~S&S&S) | (~S&S&S&S) | (S&S&~S&S); assign H = (~S&~S&~S&~S) | (~S&~S&~S&S) | (~S&S&S&S) | (S&S&~S&~S); endmodule ```

It converts a 4 bit binary into a single digit hexa, which can be displayed on the 7 seg display.

I guess I should use 16 inscances of a gated d latch, somethig like this:

``` module gated_D_latch(Clk, D, Q); input Clk, D; output Q; wire S, R, R_g, S_g, Qa, Qb /* synthesis keep */ ; assign S = D; assign R = ~D; assign S_g = ~(S & Clk); assign R_g = ~(Clk & R); assign Qa = ~(S_g & Qb); assign Qb = ~(Qa & R_g); assign Q = Qa; endmodule ```

All instances using the same Clk. But I don't know how should I wire this components up?
Honored Contributor II
564 Views

if you have a 16 bit register as the input

``` reg input_data; reg a,b,c,d; ```you can access 4bit segments of it like

``` a=input_data; b=input_data; c=input_data; d=input_data;```

a register itself is a latch. what were you planning to achieve using the gated d latch?
Honored Contributor II
564 Views

--- Quote Start ---

what were you planning to achieve using the gated d latch?

--- Quote End ---

A circuit that can store a 16 binary number.

Something like this:

img132.imageshack.us/img132/7247/circx.png

But instead of 4 instances I would use 16 so I could store 16 bits.

~CLR would be KEY0

CLK would be ~KEY1

``` module D_latch_async_rst(RST, CLK, DAT, Q); input RST, CLK, DAT; output reg Q; always @ (RST or CLK or DAT) if(~RST) Q = 1'b0; else if (CLK) Q = DAT; endmodule```
Honored Contributor II
564 Views

that should work.. i hope you realized that your circuit is level triggered and not edge triggered.. a 16 bit edge triggered d flip flop would look like this

``` module D_latch_async_rst(RST, CLK, DAT, Q); input RST, CLK; input DAT; output reg Q; always @ (posedge CLK) begin if(~RST) Q = 1'b0; else Q = DAT; end endmodule```

i hope someone will correct me if im wrong