Intel® FPGA University Program
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Problem with transferring data from different clock domains using dual_port_ram

Honored Contributor II

Hello everyone, 

I want to transfer a frame from 143Mhz clock domain to 49Mhz clock domain to view the frames through vga, 

For a test i tried to transfer a vertical and horizontal white lines to view through the vga port. But i am not getting it right. What i expect is . But what i am getting is . I don't know what i have done wrong. I am stuck  

here, If someone could help me, it would be great. 


Thank you! 


(All the VHD files are uploaded and the top level is "fifo.vhd". The board i am using is DE1-SoC)
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1 Reply
Honored Contributor II


“pll” entity is undefined in provided codes. 

Have you checked the simulation by using test bench? 


Let me know, if you need any further assistance. 


Best Regards 

Vikas Jathar  

(This message was posted on behalf of Intel Corporation)
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