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Altera_Forum
Honored Contributor I
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Some verification would be appreciated...

If someone could have a quick glance at the below, and tell me if it looks ok, I'd be very grateful. What I *think* it's doing is: 

 

- modified the 'lights' example to use SDRAM rather than on-chip RAM on the DE0 board 

- added a PLL to make the clock be 150 MHz rather than 50 MHz. 

 

Yes, I realise this is trivially simple stuff for those who know it backwards, but it's my first attempt at this whole FPGA thingy, so rather than assume it's all working, I'd prefer someone to point out if my modifications are being quietly "optimised away" ... [grin] 

 

From what I can see in the Altera Monitor, it is working - having changed the memory in the monitor project to point to the SDRAM, I can step through the (admittedly simple) code and see it working, and the addresses seem to match the SDRAM rather than the on-chip RAM so I think that *must* be working unless something is lying to me... I'm still not sure about the clock though, that seemed ... too easy... to be really working. :) 

 

The system looks like: 

 

http://www.0x0000ff.com/fpga/imgs/system.png  

 

and the top-level file looks like 

 

module lights (SW, KEY, CLOCK_50, LEDG, DRAM_CLK, DRAM_CKE, DRAM_ADDR, DRAM_BA, DRAM_CS_N, DRAM_CAS_N, DRAM_RAS_N, DRAM_WE_N, DRAM_DQ, DRAM_UDQM, DRAM_LDQM); input SW; input KEY; input CLOCK_50; output LEDG; output DRAM_ADDR; output DRAM_BA; output DRAM_CAS_N, DRAM_RAS_N, DRAM_CLK; output DRAM_CKE, DRAM_CS_N, DRAM_WE_N; output DRAM_UDQM, DRAM_LDQM; inout DRAM_DQ; // Instantiate the Nios-2 system wire pllClock; wire locked; wire phaseDone; nios_system NiosII ( .altpll_0_c0_out (pllClock), .clk_0 (CLOCK_50), .in_port_to_the_Switches (SW), .locked_from_the_altpll_0 (locked), .out_port_from_the_LEDs (LEDG), .phasedone_from_the_altpll_0 (phaseDone), .reset_n (KEY), .zs_addr_from_the_sdram_0 (DRAM_ADDR), .zs_ba_from_the_sdram_0 (DRAM_BA), .zs_cas_n_from_the_sdram_0 (DRAM_CAS_N), .zs_cke_from_the_sdram_0 (DRAM_CKE), .zs_cs_n_from_the_sdram_0 (DRAM_CS_N), .zs_dq_to_and_from_the_sdram_0 (DRAM_DQ), .zs_dqm_from_the_sdram_0 ({DRAM_UDQM, DRAM_LDQM}), .zs_ras_n_from_the_sdram_0 (DRAM_RAS_N), .zs_we_n_from_the_sdram_0 (DRAM_WE_N) ); // Use the 150 MHz clock assign DRAM_CLK = pllClock; endmodule
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Altera_Forum
Honored Contributor I
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Becareful with SDRAM controller setup, hold, wait time settings.