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Altera_Forum
Honored Contributor I
3,131 Views

Verilog code for a clock

I'm new to writing code. I'm currently working on code for a clock... a pretty standard homework application for students I know. I've been trying to teach myself verilog for sometime now, and I could some guidance.  

 

Here's part of my code for the hour part of the clock. It takes clock input that's already down to the proper timing. I'm trying to get the code to count up to 12 then reset down to 0. The outputs A and B go to a 7 segment driver, and I'm using C to count to 12 and reset. But there's obviously something wrong or I wouldn't be asking. Thanks in advance. 

-Drew 

 

 

module decimal_counter_20(A,B,CLK,RST); 

input CLK, RST; 

 

output [3:0] A; 

output [3:0] B; 

 

reg [3:0] A; 

reg [3:0] B; 

reg [4:0] C; 

 

always @ (posedge CLK or negedge RST) 

 

if (~RST)begin  

A <= 4'b0000; 

B <= 4'b0000; 

C <= 5'b00000; 

end 

 

 

else if (B < 9)begin 

B = B + 4'b0001; 

C = C + 5'b00001; 

end 

 

else if (B == 9)begin 

A = A + 4'b0001; 

B <= 4'b0000; 

end  

 

 

else if (C > 12)begin 

A <= 4'b0000; 

B <= 4'b0000; 

C <= 5'b00000; 

end  

 

 

endmodule
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2 Replies
Altera_Forum
Honored Contributor I
141 Views

Have you simulated your design? If you have, you would easily see the problem. 

 

I can't match your code with what you describe. 

 

As I understand, CLK is the hour clock, and you want to use this clock to count from 0 to 12 in a BCD sequence and display the result on two 7-segment LEDs as the hour, right? 

 

I would do it as the following: 

 

module decimal_counter_20(A,B,CLK,RST); 

input CLK, RST; 

 

output [3:0] A; // suppose A is the higher digit of hour counter 

output [3:0] B; // suppose B is the lower digit of hour counter 

 

reg [4:0] C; // hour counter from 0 ("00000")to 12 ("10010") in BCD sequence 

 

always @ (posedge CLK or negedge RST) 

 

if (~RST)  

C <= 5'b00000; 

 

else 

if (C == 5'b10010)// count to 12, reset to 0 

C <= 5'b00000; 

 

else 

if(C[3:0] == 4'b1001) //when lower digit reaches 9 

begin 

C[3:0] <= 4'b0000; //lower digit resets to 0 

C[4] <= 1'b1; //higher digit becomes 1  

end  

 

else 

C[3:0] <= C[3:0] + 4'b1; // increase by 1  

 

 

//assign the lower digit of counter to B 

assign B = C[3:0]; 

 

//A can only be either 0 or 1, so A[3:1] are always 0  

assign A[0] = C[4]; 

assign A[3:1] = 3'b000; 

 

endmodule
Altera_Forum
Honored Contributor I
141 Views

Genius... 

 

So you use C as the count... than assign A and B as outputs to the count. That makes much more sense. Its a slow learning process. Thanks for the help. 

-D
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