The device I was using was stratix iv gx, and when I was using altgx IP core, I ran into some problems. My project, in one transceiver block, requires two different reference clock frequencies (135MHZ, and 156.25MHZ), so two CMUs are required. According to the handbook, each CMU corresponds to a reset (pll-powerdown). But when I controlled pll-powerdown and pll-powedown-alt, he gave me filter error (Input port "TX-PLL-RESET"must be by the same source)
As I understand it, you observe some issue when trying to compile your design with SIV GX ALTGX with two refclk sources. Would you mind to share with me a simple test design with ALTGX which could replicate the observation so that I could further look into it? Please let me know the specific Quartus version that you are using as well. thank you.