mc 8051

[Altera_Forum]

Hello Every Body, 

 I'm new in this forum, i'm intersted in 8051 mc and i am searching for some examples on 8051 implemintation  and how would i download a software to run on it. by using cyclone ii or iii   thanks in advance

[Altera_Forum]

have a look at opencores.com there are 8051 cores.

[Altera_Forum]

You will require an editor to write code in assembly or C. 

You will have to compile it using a compiler. You will have to download it into 8051 using a programmer. You can simulate using a simulator or debugger.

[Altera_Forum]

I did some similar designs with these cores in the past but the internal memories were recognised and quartus used M4K blocks for that. so maybe some kind of quartus settings ? 

 as long as the rom is implemented as M4K memory blocks, there is no need to recompile everything. there was a thread here describing how to update the "rom" without recompiling as only the memory initial files were updated. so with the hex file it was possible to call quartus via command line to upgrade the memory inside the sof. i think it would work the way you wrote.  BTW: nice to know that sdcc is still used, i left the developer team a couple of years ago. had used sdcc all the time for real 8051 and softcore types.

[Altera_Forum]

Regarding the IRAM,  

the T51 core's IRAM (which is not the same as the integrated XRAM, that one get's mapped to M4K) originally had an assynchronous reset which, AFAIK, it's not supported by M4K.  I'm also convinced that the write-to-read behaviour, although it can be implemented using M4K and a bit more of logic, was described in VHDL in such way that Quartus does not recognize. But I'm not 100% sure.  Regarding the ROM, I got the way I wrote from the thread you're mentioning, after you kindly pointed me to it. :)

[Altera_Forum]

Hi, 

I know this thread has been inactive for years, but I have a question about the T51 Ram. Is it possible to "tap" into the internal T51 RAM from external Avalon MM? In other words, wire in an AMM master lines to the T51 RAM for direct access. Another way to accomplish this, a better way IMHO, have the T51 use onchip RAM qsys block. AMM slave exported signals from an onchip RAM block (qsys) fed directly into the T51 core so the T51 core can use it as its RAM.  The problem is I have a requirement to use 8051 (existing binary) running in it's own world and we can't rewrite it to run from NIOS, but I need to control some variables in the T51 RAM to enable/disable specific features. Previously, this was done with SPI and I'd like to stay away from that. SPI was used to simply receive address, data and loaded internal RAM contents based on the parsed data.  If OpenCores T51 isn't suitable for this, do you perhaps know of another 8051 core that can use onchip RAM as operating RAM in the same way NIOS uses onchip RAM for its memory?  Thank you.