ieee 754 for float and double divides

[tburns671]

Does ifc enforce ieee 754 for float and double divides?

I am looking for reasons that application output built using my pgi compiler doesn't match output when using my intel compiler.

I am using the pgi prebuilt blas and lapack with pgi and using the mkl when using intel.

[Steven_L_Intel1]

I don't quite understand your question or your use of the word "enforce".

IEEE 754 specifies the bit layout of floating point values, and describes operations on those values. It is more a property of the processor than the compiler as to what floating point format is used. Intel processors use IEEE 754 floating point.

Now it is true that on IA-32, floating point operations tend to get carried out in double-precision or even extended precision registers, unless SSE/SSE2 is used. This can sometimes lead to small differences when compared to other architectures that do operations in the declared precision.

Steve

[tburns671]

Thanks for the lesson. I think you answered my question.
thanks again.

[TimP]

When using SSE vector code, the options -mp1 or -prec_div, or Windows equivalents, require use of IEEE 754 compliant divide. The default vectorized iterative sequence may round less accurately.
I don't know whether PGI BLAS is built with SSE. With Intel MKL, you can choose SSE or x87 versions. The x87 versions should have fewer roundoff errors, as Steve mentioned. Both types of operation are in accord with IEEE 754, but some people mean strict single precision when they ask questions such as yours.