Building OpenCL kernel with v18.1.0 fails

[LSolis]

Hi, I am using Intel FPGA OpenCL SDK Version 18.1.0 Build 222 Pro Edition.

My problem is that building FPGA binaries fails, althought I used to build successfully the very same design with previous releases (16.0, 16.1, 17.1). Emulation runs fine in all mentioned releases.

I am targetting the Nallatech device "p520_max_sg280l". Their documentation strongly suggests to use a previous release 18.0.1 Build 261 (I don't have it installed yet), but I thought v18.1.0 should work since it is advertised as fully backwards compatible with Quartus v18.0 & 17.1.1 here: https://www.intel.com/content/www/us/en/software/programmable/sdk-for-opencl/overview.html

Any hint would be greatly appreciated!

Here is the output of building process:

aoc -board=p520_max_sg280l device/Krnl_GA.cl -o bin_hw/Krnl_GA.aocx -DFIXED_POINT_CONFORM -DFIXED_POINT_LS1 -DFIXED_POINT_LS2 -DFIXED_POINT_LS3 -DFIXED_POINT_LS4 -DFIXED_POINT_LS5 -DFIXED_POINT_LS6 -DFIXED_POINT_LS7 -DFIXED_POINT_LS8 -DFIXED_POINT_LS9 -DSINGLE_COPY_POP_ENE -const-cache-bytes=12288 -fp-relaxed -fpc aoc: Running OpenCL parser.... aoc: OpenCL parser completed successfully. aoc: Linking Object files.... aoc: Optimizing and doing static analysis of code... aocl-opt: /build/swbuild/SJ/nightly/18.1/222/l64/p4/acl/llvm/lib/IR/Instructions.cpp:2565: static llvm::CastInst* llvm::CastInst::Create(llvm::Instruction::CastOps, llvm::Value*, llvm::Type*, const llvm::Twine&, llvm::Instruction*): Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed. /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(_ZN4llvm3sys15PrintStackTraceERNS_11raw_ostreamE+0x2a)[0x7f104830871a] /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(_ZN4llvm3sys17RunSignalHandlersEv+0x3e)[0x7f104830645e] /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(+0xb0b804)[0x7f1048306804] /lib64/libpthread.so.0(+0x120c0)[0x7f10475ee0c0] /lib64/libc.so.6(gsignal+0x10b)[0x7f1046925eab] /lib64/libc.so.6(abort+0x123)[0x7f10469105b9] /lib64/libc.so.6(+0x21491)[0x7f1046910491] /lib64/libc.so.6(+0x2f612)[0x7f104691e612] /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(_ZN4llvm8CastInst6CreateENS_11Instruction7CastOpsEPNS_5ValueEPNS_4TypeERKNS_5TwineEPS1_+0x27f)[0x7f10483fc38f] /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(+0x1d6791c)[0x7f104956291c] /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(+0x1d6bfe1)[0x7f1049566fe1] /opt/cad/altera/altera-18.1/hld/llvm/bin/../lib/libLLVM-6.0.so(_ZN4llvm6legacy15PassManagerImpl3runERNS_6ModuleE+0x2d8)[0x7f104841c6b8] /opt/cad/altera/altera-18.1/hld/linux64/bin/../../llvm/bin/aocl-opt(main+0x236b)[0x55a3b53c421b] /lib64/libc.so.6(__libc_start_main+0xeb)[0x7f104691211b] /opt/cad/altera/altera-18.1/hld/linux64/bin/../../llvm/bin/aocl-opt(+0x27fad)[0x55a3b53c4fad] Stack dump: 0. Program arguments: /opt/cad/altera/altera-18.1/hld/linux64/bin/../../llvm/bin/aocl-opt -march=fpga -O3 -board /home/wimi/lvs/BSP_AOC_NALLA520/nalla_pcie/hardware/p520_max_sg280l/board_spec.xml --cic-const-cache-bytes=16384 -fp-relaxed=true -fpc=true -dbg-info-enabled --soft-elementary-math=false -pass-remarks-output=pass-remarks.yaml Krnl_GA.fpga.bc -o Krnl_GA.kwgid.bc 1. Running pass 'Fixup for user specified Memory Attributes' on module 'Krnl_GA.fpga.bc'. Error: Optimizer FAILED. Refer to Krnl_GA/Krnl_GA.log for details.   make: *** [Makefile:836: hw] Error 1

[HRZ]

Your kernel compilation is crashing due to some bug in the OpenCL compiler; this has nothing to do with the BSP you are using since the process does not even reach the placement and routing stage. You can try installing the 18.1.1 update and see if it fixes your problem. If not, based on your tests that the same kernel works fine in the older versions of the compiler, this is likely a regression in the newer version(s). If that is the case, then you will probably have to wait until some moderator in the forum escalates the problem to the engineering team.

[LSolis]

Thanks for the feedback @HRZ​ ,

I've just tried with Version 18.1.1 Build 263 Pro Edition, but same error appear.

Strange, I am currently trying also with v18.0, and build seems to be progressing (not yet finished).

[LSolis]

Btw @HRZ​ , any suggestion on how to notify a moderator about this (if possible)?

[HRZ]

It seems the forum has the possibility of sending messages to other users. I haven't tried but you can try sending a message to one of the moderators who are more active in this section of the forum. However, if 18.0 works for you, you might as well go with that for the time being; there have hardly been any major improvements between the recent versions of the OpenCL compiler anyway.

[MuhammadAr_U_Intel]

Hi, Looking at the compiler output you shared it seems like a compiler bug. If possible you can share the kernel code and steps you followed to replicate the issue with me (here or in private message), in order for me to replicate this and report it to Engineering team. Thanks, Arslan

[LSolis]

Hi @MUsman​ ,

I've sent you a private message.

Thanks!

Leonardo

[Gigi]

Hi @LSolis​ ,

The 520 OpenCL Board Support packages for Nallatech (now BittWare) boards have a 1-to-1 relationship with the version of Quartus for which they were built. The version of the Quartus/OpenSDK documented on the Support Lounge (Developer Site) must be used to compile the user designs. The Arria 10 or Stratix 10-based OpenCL BSPs do not support the auto-migration feature to a newer version of tools (only StratixV BSPs support auto-migration).

Please install the version of Quartus listed on the website and log a support ticket with BittWare is you still see an issue then.

Thanks,

G

[MuhammadAr_U_Intel]

Hi, We have looked into this specific case by implementing kernel targeting Arria10 BSP, OpenCL compiler still gives Error and is feedback to Engineering team. Thanks, Arslan