Hard IP reconfiguration interface

[sgr]

Hi,

Can anyone suggest to me how to configure the PCIe Configuration register using L- and H-tile Avalon Streaming PCIe hard IP?

I have gone through the Hard IP reconfiguration interface to configure the Configuration space register, but I am not able to get how to configure it, can anyone please sort me out by any example design or any required document?

Thanks

[wchiah]

Hi,

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

Best regards,

Wincent_C

[wchiah]

Hi

To access the Hard IP Reconfiguration block, IP Catalog >> Avalon®-ST Intel® Stratix® 10 Hard IP for PCI Express* OR Avalon®-MM Intel® Stratix® 10 Hard IP for PCI Express*>> "Configuration, Debug and Extension Options" tab >> turn on "Enable hard IP dynamic reconfiguration of PCIe read-only registers". To dynamically modify the value of configuration registers that are read-only at run time, refer to the "Hard IP Reconfiguration" section of the respective user guide.

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this IPS case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi,

I strongly believe my previous reply answered your question. 

We do not receive any response from you to the previous answer that I provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel