Can anyone suggest to me how to configure the PCIe Configuration register using L- and H-tile Avalon Streaming PCIe hard IP?
I have gone through the Hard IP reconfiguration interface to configure the Configuration space register, but I am not able to get how to configure it, can anyone please sort me out by any example design or any required document?
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To access the Hard IP Reconfiguration block, IP Catalog >> Avalon®-ST Intel® Stratix® 10 Hard IP for PCI Express* OR Avalon®-MM Intel® Stratix® 10 Hard IP for PCI Express*>> "Configuration, Debug and Extension Options" tab >> turn on "Enable hard IP dynamic reconfiguration of PCIe read-only registers". To dynamically modify the value of configuration registers that are read-only at run time, refer to the "Hard IP Reconfiguration" section of the respective user guide.
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