Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
677 Discussions

Hello Everyone, Is it possible to disable the loop pipelining completely? I tried using the max_concurrency Pragma to set the concurrency to 1 but still in the report I see that the loops are marked as pipelined

GSing13
Novice
1,491 Views
 
0 Kudos
2 Replies
HRZ
Valued Contributor III
1,051 Views

No, it is not possible to disable loop pipelining, and there is probably little to no reason to do so either. Why do you want to disable pipelining?

 

The max_concurrency parga is designed for a different reason (controlling replication factor for multi-ported RAM/ROM buffers used in a single work-item loop by limiting number of loop iteration that can be in-flight concurrently).

0 Kudos
Kenny_Tan
Moderator
1,051 Views
Is there any update?
0 Kudos
Reply