- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I want to modifying the Verilog code in the output of the OpenCL parser. Which is generated by the command "aoc -c -g device/vector_add.cl". And then I want to generate .aocx file from the folder. Anyone know how to do that ?
thank you !!
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
You can do that, however, this might change the functionality of the design. Furthermore, it might bring some timing issues which will increase the design complexity.
Thanks

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page