HI,
We are in need to counting both poedge and negedge. our master clock is 125mhz (8ns). we need to count every posedge (4ns) and negedge (4ns). in quartus SW both posedge and negedge is not working. we have tried to invert clk and give both as posedge, that is also not working. please suggest better way to use dual edge counter.
assign clk_n = ~clk; // used to check both posedge and negedge
always @(posedge clk or posedge clk_n) begin
N=ip_freq/(freq * multiple); // counter value calc
if (rst) begin
counter <= 16'b0;
end
else begin
if(pulse_done)begin
F <= N; // if pulse_done=1 then load counter
end
if (counter == F) begin
pulse_enb <=1'b1; // enable wave generation module
counter <= 16'b0;
pulse_done <= 1'b1;
end
else begin
pulse_done <= 1'b0;
counter <= counter + 1'b1;
pulse_enb <=1'b0;
end
end
end
