Quartus 16.0 cannot fin port "clock" in the synthesized RTL files

[SXian3]

Hi, 

I was using AOC 16.0.2 to synthesize a OpenCL kernel. I am able to run through the first stage compilation and see the HLS resource estimate. However, Quartus complains that some ports were not found in the `quartus_sh_compile.sh`. 

Warning (13461): Verilog HDL Parameter Declaration warning at altera_avalon_mm_cci_bridge.v(156): Parameter Declaration in module "altera_avalon_mm_cci_bridge" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/board/altera_avalon_mm_cci_bridge_131/synth/altera_avalon_mm_cci_bridge.v Line: 156

Warning (13461): Verilog HDL Parameter Declaration warning at cci_requester.v(175): Parameter Declaration in module "cci_requester" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/board/altera_avalon_mm_cci_bridge_131/synth/cci_requester.v Line: 175

Info: Elaborating from top-level entity "kernel_wrapper"Info (18235): Library search order is as follows: "board; altera_mm_interconnect_160; altera_merlin_multiplexer_160; altera_avalon_dc_fifo_160; altera_merlin_master_translator_160; altera_merlin_demultiplexer_160; altera_avalon_sc_fifo_160; altera_avalon_st_adapter_160; error_adapter_160; altera_merlin_slave_translator_160; altera_merlin_width_adapter_160; altera_merlin_slave_agent_160; altera_merlin_master_agent_160; altera_merlin_router_160; altera_merlin_traffic_limiter_160; altera_avalon_st_pipeline_stage_160; altera_reset_controller_160; altera_merlin_burst_adapter_160; acl_irq_to_polling_slave_100; altera_avalon_mm_bridge_160; altera_avalon_mm_clock_crossing_bridge_160; altera_irq_clock_crosser_160; sw_reset_100; altera_avalon_onchip_memory2_160; version_id_100; acl_kernel_clk_a10_151; altera_iopll_160; acl_timer_100; altera_pll_reconfig_160; pll_lock_avs_100; altera_irq_mapper_160; kernel_interface_151; mem_org_mode_100; altera_avalon_st_handshake_clock_crosser_160; altera_address_span_extender_160; altera_irq_bridge_160; global_routing_reset_100; cci_interface_10; altera_avalon_mm_cci_bridge_131; kernel_system; kernel_system_140; cra_ring_root_10; cra_ring_node_10; acl_rom_module_10; cra_ring_rom_10". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER.

Error (13305): Verilog HDL error at kernel_system.v(324): can't find port "clock" File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 324
Info (16867): Verilog HDL info at kernel_system.v(6): kernel_system is declared here File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 6
Error (13305): Verilog HDL error at kernel_system.v(325): can't find port "resetn" File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 325
Info (16867): Verilog HDL info at kernel_system.v(6): kernel_system is declared here File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 6
Error (13305): Verilog HDL error at kernel_system.v(326): can't find port "clock2x" File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 326
Info (16867): Verilog HDL info at kernel_system.v(6): kernel_system is declared here File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 6
Error (13305): Verilog HDL error at kernel_system.v(327): can't find port "avs_test_cra_read" File: /homes/sx233/temp.bdx.hw.BASE_1D.bdx/kernel/kernel_system/synth/kernel_system.v Line: 327

I assumed those ports should be taken care of by the compiler. Any thoughts how to solve it?