Timing Analysis not met on holdtime

[KWang97]

Hold time slack is minus, so how to solve this problem? How can I meet Timing requirements. Some specific files about my project are attached. Please download and help me analyze it and hope for your solutions. Thanks very much!

[KWang97]

“FPGA_CLOCK_25MHZ” is the 25MHZ input clock， “pll_clk_out_50 ” is clock generated by PLL IP which is 50MHz, and “pll_clk_out_50 ” didn't meet the Timing analysis.

[KhaiChein_Y_Intel]

Hi,

Can you provide the design for investigation? May I know the software editon and version?

Thanks.

[KWang97]

quartus prime standard 18.1。 While the design can't be shared for confidential reason.

Hope you could provide solutions to improve negative hold time slack. The setup time slack is ok.

Thanks!

[KhaiChein_Y_Intel]

Hi,

It is difficult to investigate the timing violation without the design. Can you report the failing path in details for both setup and hold?

Thanks.

[KWang97]

How to see failing path in details for both setup and hold? I don't know how to get the failing path, how to operate to get it? Thanks!

[KhaiChein_Y_Intel]

Hi,

You may report setup summary > report timing on the failing clock > export the report

Thanks.

[KWang97]

Hi Thanks for your reply. But I can’t see where is “report timing on the failing clock”. Could you please the specific steps with pictures showing where can I find these items.

[KhaiChein_Y_Intel]

Hi,

You may right click on the failing clock > Report Timing

 

Thanks.

[KWang97]

Hi Thanks. I can’t find acq_trigger_in_reg[2]? Where is it? And how to improve holdtime slack?

[KhaiChein_Y_Intel]

Hi,

May I know where do you want to find acq_trigger_in_reg[2], in RTL Viewer, Chip Planner, Timing Analyzer, or others?

It is difficult to improve the slack without looking into the design. May I request the timing report for the failing path in details?

Thanks.

[KWang97]

Please check the report attached

[KWang97]

posted a file.

[KhaiChein_Y_Intel]

Hi,

May I have the report for setup on the same path?

Thanks.

[KWang97]

Please download the setup report attched.

[KhaiChein_Y_Intel]

Hi,

You could try overconstraining by adding the following to your sdc file

set current_exe $::TimeQuestInfo(nameofexecutable)

if { $current_exe == "quartus_fit" } {

set_min_delay -from -to <value>

post_message -type info "Overconstraining path"

}

https://fpgawiki.intel.com/wiki/Timing_Constraints#Overconstrain_path

Thanks

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

[KWang97]

No. Thanks! Please leave it out for now. Best Regards! Kensou