Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
679 Discussions

Timing constraints on PLL

Bhavana_t
Beginner
753 Views

Do we have to constrain the clocks that are generated through the PLL?

I am currently using Intel MAX 10 FPGA.

0 Kudos
1 Solution
RichardTanSY_Intel
742 Views

Yes, you may checkout the User Guide below. 

 https://www.intel.com/content/www/us/en/docs/programmable/683081/17-1-1/pll-clocks.html

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

View solution in original post

2 Replies
RichardTanSY_Intel
743 Views

Yes, you may checkout the User Guide below. 

 https://www.intel.com/content/www/us/en/docs/programmable/683081/17-1-1/pll-clocks.html

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

RichardTanSY_Intel
723 Views

I’m believed I have addressed your question. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

Reply