Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
676 Discussions

Why does aoc set ii to 6 when I use high clock frequencies?

Björne
Novice
1,934 Views

I have a simple toy that I want to run at 1000 MHz kernel that doesn't do much:

 

__attribute__((uses_global_work_offset(0)))
__attribute__((max_global_work_dim(0)))
__kernel void
netsim(
__global const volatile float * restrict gl_vm
) {
float vm[50000];
#pragma ii 1
#pragma ivdep
#pragma speculated_iterations 64
for (int i = 0; i < 50000; i++) {
vm[i] = gl_vm[i];
}
}

 

According to the report (see screenshot), II=6 and latency=927. Why can't the compiler lower the latency and set II to 1 here?

0 Kudos
10 Replies
BoonBengT_Intel
Moderator
1,904 Views

Hi @Björne,


Thank you for posting in Intel community forum and hope all is well.

To help us understand the situation better, may I know what are the tools and also hardware that you are using in this situation? Any error message that you are seeing?

Also is there any references design that you are referring?

Hope to hear from you soon.


Best Wishes

BB


0 Kudos
Björne
Novice
1,879 Views

The hardware is Agilex 7 F-Series. The software is aoc Version 21.2.0 Build 67.4 Pro Edition. No error messages or anything like that. I know 1000 MHz is much for the fpga but I'm seeing the same issue even with 700 MHz which the fpga should be able to handle.

0 Kudos
BoonBengT_Intel
Moderator
1,847 Views

Hi @Björne,


Noted on the hardware involved and software version mention, to further clarify are you using the Intel OpenCL Compiler or Intel HLS compiler? I believe above are some custom code which you have written with the purpose to figure out the clock frequencies, it would be very helpful to provide us what are the steps to compile the example too.

Hope to hear from you soon.


Best Wishes

BB



0 Kudos
BoonBengT_Intel
Moderator
1,777 Views

Hi @Björne,


Good day, just following up on the previous clarification.

By any chances did you managed to look into it?

Hope to hear from you soon.


Best Wishes

BB


0 Kudos
Björne
Novice
1,736 Views

Hi @BoonBengT_Intel , I'm using the Intel OpenCL Compiler. So the reports I'm referring to are those produced by that compiler. I'm trying to get it to make designs with 700 MHz.

 

 

0 Kudos
BoonBengT_Intel
Moderator
1,623 Views

Hi @Björne,


Thanks for confirming the tools involved, is there any references design with BSP that you are referring to?

Also what are the compilation involved? This would be helpful information for us to try the mention design.

Hope to hear from you soon.


Best Wishes

BB



0 Kudos
BoonBengT_Intel
Moderator
1,339 Views

Hi @Björne,


Good day, just following up on the previous clarification.

By any chances did you managed to look into it?

Hope to hear from you soon.


Best Wishes

BB


0 Kudos
BoonBengT_Intel
Moderator
1,337 Views

Hi @Björne,


As mention the tool involved are Intel OpenCL, the product mention has been deprecated and are now on the best effort support only. Hence would recommended to move to the newer and similar tools Intel OneAPI.

To add on to the mention request, the clock frequency for openCL are set in the BSP, hence changing that is not recommended as that required a separate BSP customization flow. However if some reason the kernel code ar not able to run with the mention frequency, you can look into the OpenCL kernel clock generator, as mention in the link below:

- https://www.intel.com/content/www/us/en/docs/programmable/683398/18-1/opencl-kernel-clock-generator-opencl.html

Hope that clarify.


Best Wishes

BB


0 Kudos
Björne2
Beginner
1,311 Views

I'm not sure what you mean by reference design. The kernel I'm compiling is the one shown in the source code. The compile command I'm using is: aoc -bsp-flow=flat -seed=251 -parallel=16 -ffp-contract=fast -ffp-reassociate -clock=1000MHz -O3 test.cl where 251 is just some random number I picked.

0 Kudos
BoonBengT_Intel
Moderator
883 Views

Hi @Björne,


References design are those design that are created and tested by Intel. Hence those design would be highly recommended to start with for better understand on our product. From the earlier post, you can try on the kernel clock generator. Hope that clarify, as question may been clarify this thread will be transitioned to community support for further help on doubts in this thread. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

Thank you for the questions and as always pleasure having you here. 


Best Wishes

BB


0 Kudos
Reply