Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.

Any documentation to TSX?

AaronSu
Beginner
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Are there any documentation describing how the causes of transaction aborts (e.g. conflicts, capacity aborts) matches with abort codes?

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Roman_D_Intel
Employee
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Hi AaronSu,

the TSX (RTM) transaction abort status definition is described in Section "17.3. 5 RTM Abort Status Definition" of Intel® 64 and IA-32 Architectures Software Developer’s Manual available at www.intel.com/sdm . More details can be found in "CHAPTER 8
INTEL® TRANSACTIONAL SYNCHRONIZATION EXTENSIONS (INTEL® TSX) OPTIMIZATIONS": Intel 64 and IA-32 Architectures Optimization Reference Manual Volume 2: Earlier Generations of Intel 64 and IA-32 Processor Architectures, and Throughput and Latency, v50

available from https://www.intel.com/content/www/us/en/developer/articles/technical/intel64-and-ia32-architectures-optimization.html 

 

Best regards,

Roman

 

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