Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.

Cache L1 , L2 , L3 ?

RBato
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jimdempseyatthecove
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gaston-hillar
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Rafal,

The following article written by Chris Gottbrath a few years ago and published on Dr. Dobb's is very useful to understand processor caches. It was written before Intel launched the first Xeon Phi. However, it is still very useful. The following is the link: http://www.drdobbs.com/parallel/cache-friendly-code-solving-manycores-ne/240012736

 

 

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gaston-hillar
Valued Contributor I
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Rafal,

Another article that you must read and is written by the same person that provided the first answer for your thread: Jim Dempsey (jimdempseytatthecove).

The article has a few years but it is a must read (short but useful article). Superscalar Programming with HyperThreading and Shared Cache Systems

 

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