Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
1135 ディスカッション

Cycle counts of the new Westmere instructions

Cryptographer
ビギナー
734件の閲覧回数
How many cycles do the new instructions require
and can they be paired with other intructions?

aesimc
aeskeygenassist
aesenc
aesenclast
aesdec
aesdeclast
pclmulqdq
0 件の賞賛
2 返答(返信)
capens__nicolas
新規コントリビューター I
734件の閲覧回数
The AES-NI white paper has some performance results from which you could estimate the instruction latencies: http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-aes-instructions-set/. It explicitly mentions that they are pipelined too.

You can expect pclmulqdq to perform the same as other vector multiplications.
neni
新規コントリビューター II
734件の閲覧回数

it changes by impl, you can take your aes kernel(s) and run it through the CodenAnalyzer to understand tput, latency, etc
http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/

返信