Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.

Cycle counts of the new Westmere instructions

Cryptographer
初學者
730 檢視
How many cycles do the new instructions require
and can they be paired with other intructions?

aesimc
aeskeygenassist
aesenc
aesenclast
aesdec
aesdeclast
pclmulqdq
0 積分
2 回應
capens__nicolas
新貢獻者 I
730 檢視
The AES-NI white paper has some performance results from which you could estimate the instruction latencies: http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-aes-instructions-set/. It explicitly mentions that they are pipelined too.

You can expect pclmulqdq to perform the same as other vector multiplications.
neni
新貢獻者 II
730 檢視

it changes by impl, you can take your aes kernel(s) and run it through the CodenAnalyzer to understand tput, latency, etc
http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/

回覆