Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
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Cycle counts of the new Westmere instructions

Cryptographer
Beginner
168 Views
How many cycles do the new instructions require
and can they be paired with other intructions?

aesimc
aeskeygenassist
aesenc
aesenclast
aesdec
aesdeclast
pclmulqdq
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2 Replies
capens__nicolas
New Contributor I
168 Views
The AES-NI white paper has some performance results from which you could estimate the instruction latencies: http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-aes-instructions-set/. It explicitly mentions that they are pipelined too.

You can expect pclmulqdq to perform the same as other vector multiplications.
neni
New Contributor II
168 Views

it changes by impl, you can take your aes kernel(s) and run it through the CodenAnalyzer to understand tput, latency, etc
http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/

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