Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
1135 Discussions

Cycle counts of the new Westmere instructions

Cryptographer
Beginner
789 Views
How many cycles do the new instructions require
and can they be paired with other intructions?

aesimc
aeskeygenassist
aesenc
aesenclast
aesdec
aesdeclast
pclmulqdq
0 Kudos
2 Replies
capens__nicolas
New Contributor I
789 Views
The AES-NI white paper has some performance results from which you could estimate the instruction latencies: http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-aes-instructions-set/. It explicitly mentions that they are pipelined too.

You can expect pclmulqdq to perform the same as other vector multiplications.
0 Kudos
neni
New Contributor II
789 Views

it changes by impl, you can take your aes kernel(s) and run it through the CodenAnalyzer to understand tput, latency, etc
http://software.intel.com/en-us/articles/intel-architecture-code-analyzer/

0 Kudos
Reply