There are a couple of incorrect links (references) to "Figure 6-4. Stack Usage on Transfers to Interrupt and Exception-Handling Routines" in the Intel® 64 and IA-32 Architectures Software Developer’s Manual.
Under "6.12.1 Exception- or Interrupt-Handler Procedures" there are couple of links to the Figure 6-4 as below but are actually linked to "Table 6-4. Interrupt and Exception Classes".
The processor then saves the current state of the EFLAGS, CS, and EIP registers on the new stack (see Figures 6-4).
a. The processor saves the current state of the EFLAGS, CS, and EIP registers on the current stack (see Figures 6-4).