Intel® ISA Extensions
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Penalty for 256-bit loads and stores with cache line splits

jeremyweek
Beginner
134 Views
Hi,

I was wondering what the penalty, in clock cycles, is for doing 256-bit loads and stores when there is
a cache line split?

Thanks!

-Jeremy
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1 Reply
TimP
Black Belt
134 Views
For Sandy Bridge, the compilers avoid a cache line split on AVX-256 by always splitting explicitly into AVX-128 instructions, which are expected to be faster in that case. You would have to write intrinsics to test it. Your guess about other AVX CPUs is as good as mine.
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