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Questions Regarding DDIO and Cache Control Bit in DSA with DMA engine API

yun3319
Novice
‎10-10-2024 12:12 AM
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Hello,

 

I am currently performing DMA memcpy operations using the DMAengine API in the Linux kernel and have learned that DSA allows enabling and disabling DDIO on a per-request basis. The DSA specification mentions that the Cache Control bit can be used to manage DDIO behavior. I have two questions regarding this:

  1. The Cache Control bit is present in both the descriptor field and the GENCAP register. What is the functional difference between these two Cache Control bits in terms of DDIO management?

  2. It seems that there is no code to set the cache control flag(IDXD_OP_FLAG_CC) in the linux kernel 6.6.0, and by default, the cache control flag is set to 0. In this case, does only DDIO setting determine whether the LLC is used in the system?

I would appreciate any guidance on this. Thank you!

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