Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.

the issue about APIC drop msix interrupt


hello, I have a difficult problem,.scenes are as follows:

the hardware env is Intel(R) Xeon(R) CPU E5-2609 v2 @ 2.50GHz, a Altera FPGA board. 

the os is Linux debian-rss 3.16.7-ckt7

FPGA create 32 DMA transfer to cpu, generate a interrupt per transfer.

This 32 interrput distribution to 8 diffirent msix IRQ.

According to APIC spec, each interrupt maybe one in ISR, one in IRR,the third maybe dropped.

But now i distribution 2 interrputs to each IRQ, why maybe dropped interrputs?

can we modirfy APIC IRR ,let it pendding more interrupts ?

also is this releated to PCIE traffic class?


Very much looking forward to your reply



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