Thanks to all for the replies. I do not have the 7.1 libraries for Windows, just Linux. Here is my code. From this and the previously provided debug output you should see the CPU type. Clearly not a Pentium 4.
ippInit();
if (!m_bDisplayedIPPCPUFeatures)
{
m_bDisplayedIPPCPUFeatures = true;
DisplayIPPCPUFeatures();
}
void DisplayIPPCPUFeatures()
{
IppStatus l_Status;
//Can be useful for debugging/profiling
//Get version info
//COMMENTED OUT BECAUSE ippiGetLibVersion IS UNRESOLVED
// const IppLibraryVersion *lib = ippiGetLibVersion();
// printf("%s %s\n", lib->Name, lib->Version);
switch (ippGetCpuType())
{
default:
case ippCpuUnknown: printf("Unknown (%x)\n", (unsigned)ippGetCpuType()); break;
case ippCpuPP: printf("Intel(R) Pentium(R) processor\n"); break;
case ippCpuPMX: printf("Pentium(R) processor with MMX(TM) technology\n"); break;
case ippCpuPPR: printf("Pentium(R) Pro processor\n"); break;
case ippCpuPII: printf("Pentium(R) II processor\n"); break;
case ippCpuPIII: printf("Pentium(R) III processor and Pentium(R) III Xeon(R) processor\n"); break;
case ippCpuP4: printf("Pentium(R) 4 processor and Intel(R) Xeon(R) processor\n"); break;
case ippCpuP4HT: printf("Pentium(R) 4 Processor with HT Technology\n"); break;
case ippCpuP4HT2: printf("Pentium(R) 4 processor with Streaming SIMD Extensions 3\n"); break;
case ippCpuCentrino: printf("Intel(R) Centrino(TM) mobile technology\n"); break;
case ippCpuCoreSolo: printf("Intel(R) Core(TM) Solo processor\n"); break;
case ippCpuCoreDuo: printf("Intel(R) Core(TM) Duo processor\n"); break;
case ippCpuITP: printf("Intel(R) Itanium(R) processor\n"); break;
case ippCpuITP2: printf("Intel(R) Itanium(R) 2 processor\n"); break;
case ippCpuEM64T: printf("Intel(R) 64 Instruction Set Architecture (ISA)\n"); break;
case ippCpuC2D: printf("Intel(R) Core(TM) 2 Duo processor\n"); break;
case ippCpuC2Q: printf("Intel(R) Core(TM) 2 Quad processor\n"); break;
case ippCpuPenryn: printf("Intel(R) Core(TM) 2 processor with Intel(R) SSE4.1\n"); break;
case ippCpuBonnell: printf("Intel(R) Atom(TM) processor\n"); break;
case ippCpuNehalem: printf("Intel(R) Core(TM) i7 processor\n"); break;
case ippCpuNext: printf("Next\n"); break;
case ippCpuSSE: printf("Processor supports Streaming SIMD Extensions instruction set\n"); break;
case ippCpuSSE2: printf("Processor supports Streaming SIMD Extensions 2 instruction set\n"); break;
case ippCpuSSE3: printf("Processor supports Streaming SIMD Extensions 3 instruction set\n"); break;
case ippCpuSSSE3: printf("Processor supports Supplemental Streaming SIMD Extension 3 instruction set\n"); break;
case ippCpuSSE41: printf("Processor supports Streaming SIMD Extensions 4.1 instruction set\n"); break;
case ippCpuSSE42: printf("Processor supports Streaming SIMD Extensions 4.2 instruction set\n"); break;
case ippCpuAVX: printf("Processor supports Advanced Vector Extensions instruction set\n"); break;
case ippCpuAES: printf("Processor supports AES New Instructions\n"); break;
case ippCpuF16RND: printf("Processor supports RDRRAND & Float16 instructions\n"); break;
case ippCpuAVX2: printf("Processor supports Advanced Vector Extensions 2 instruction set\n"); break;
case ippCpuX8664: printf("Processor supports 64 bit extension\n"); break;
}
printf(" %d cores on die\n", ippGetNumCoresOnDie());
int l_iMaxCacheSizeB = 0;
l_Status = ippGetMaxCacheSizeB (&l_iMaxCacheSizeB);
switch (l_Status)
{
case ippStsNullPtrErr: printf("ippGetMaxCacheSizeB ippStsNullPtrErr\n"); break;
case ippStsNotSupportedCpu: printf("ippGetMaxCacheSizeB ippStsNotSupportedCpu\n"); break;
case ippStsUnknownCacheSize: printf("ippGetMaxCacheSizeB ippStsUnknownCacheSize\n"); break;
default: printf("ippGetMaxCacheSizeB unexpected status %#x\n", (unsigned)l_Status); break;
case ippStsNoErr: printf("ippGetMaxCacheSizeB %d k\n", l_iMaxCacheSizeB / 1024); break;
}
Ipp64u l_FeatureMaskAvailable = 0;
Ipp64u l_FeatureMaskEnabled = 0;
Ipp32u l_CpuidInfoRegs[4] = {0};
//Get CPU features available with selected library level
ippGetCpuFeatures (&l_FeatureMaskAvailable, l_CpuidInfoRegs);
//Get CPU features enabled with selected library level
l_FeatureMaskEnabled = ippGetEnabledCpuFeatures();
printf("ippGetCpuFeaturesAvaileble %#llx l_FeatureMaskEnabled %#llx\n",l_FeatureMaskAvailable, l_FeatureMaskEnabled);
printf("MMX %c %c\n", (l_FeatureMaskAvailable & ippCPUID_MMX)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_MMX)?'Y':'N');
printf("SSE %c %c\n", (l_FeatureMaskAvailable & ippCPUID_SSE)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_SSE)?'Y':'N');
printf("SSE2 %c %c\n", (l_FeatureMaskAvailable & ippCPUID_SSE2)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_SSE2)?'Y':'N');
printf("SSE3 %c %c\n", (l_FeatureMaskAvailable & ippCPUID_SSE3)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_SSE3)?'Y':'N');
printf("SSSE3 %c %c\n", (l_FeatureMaskAvailable & ippCPUID_SSSE3)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_SSSE3)?'Y':'N');
printf("MOVBE %c %c\n", (l_FeatureMaskAvailable & ippCPUID_MOVBE)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_MOVBE)?'Y':'N');
printf("SSE41 %c %c\n", (l_FeatureMaskAvailable & ippCPUID_SSE41)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_SSE41)?'Y':'N');
printf("SSE42 %c %c\n", (l_FeatureMaskAvailable & ippCPUID_SSE42)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_SSE42)?'Y':'N');
printf("AVX %c %c\n", (l_FeatureMaskAvailable & ippCPUID_AVX)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_AVX)?'Y':'N');
printf("AVX(OS) %c %c\n", (l_FeatureMaskAvailable & ippAVX_ENABLEDBYOS)?'Y':'N', (l_FeatureMaskEnabled & ippAVX_ENABLEDBYOS)?'Y':'N');
printf("AES %c %c\n", (l_FeatureMaskAvailable & ippCPUID_AES)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_AES)?'Y':'N');
printf("CLMUL %c %c\n", (l_FeatureMaskAvailable & ippCPUID_CLMUL)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_CLMUL)?'Y':'N');
printf("ABR %c %c\n", (l_FeatureMaskAvailable & ippCPUID_ABR)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_ABR)?'Y':'N');
printf("RDRRAND %c %c\n", (l_FeatureMaskAvailable & ippCPUID_RDRRAND)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_RDRRAND)?'Y':'N');
printf("F16C %c %c\n", (l_FeatureMaskAvailable & ippCPUID_F16C)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_F16C)?'Y':'N');
printf("AVX2 %c %c\n", (l_FeatureMaskAvailable & ippCPUID_AVX2)?'Y':'N', (l_FeatureMaskEnabled & ippCPUID_AVX2)?'Y':'N');
}