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EDing
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10AS027E3F29I2SG simulation error

 

#   Time: 0 ps Iteration: 0 Instance: /bsm_epl_pcl_egl_bsf_tst/uut/b2v_inst File: /build/swbuild/SJ/nightly/18.0std/614/l64/work/modelsim/eda/sim_lib/altera_mf.v

# ** Error: (vsim-3935) ../../BSM_EPL_PCL_EGL.vhd(1316): Port 'A_OUT' not found in the connected module.

#   Time: 0 ps Iteration: 0 Instance: /bsm_epl_pcl_egl_bsf_tst/uut/b2v_inst File: /build/swbuild/SJ/nightly/18.0std/614/l64/work/modelsim/eda/sim_lib/altera_mf.v

# ** Error: (vsim-3935) ../../BSM_EPL_PCL_EGL.vhd(1316): Port 'A_IN' not found in the connected module.

#   Time: 0 ps Iteration: 0 Instance: /bsm_epl_pcl_egl_bsf_tst/uut/b2v_inst File: /build/swbuild/SJ/nightly/18.0std/614/l64/work/modelsim/eda/sim_lib/altera_mf.v

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EDing
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What's missing here to set up the simulation with Qsys IP? Thanks!​

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Hi,

 

Which IP are you trying to simulate ?

Can you share some more details, what are the steps you have followed to bring up simulation ?

 

Intel FPGA IP's comes with auto-generate script located in directory <ip name>/simulation/ that can be used to bring up the simulation.

 

https://www.intel.com/content/www/us/en/programmable/documentation/mwh1409960636914.html#mwh14099582...

 

Let me know if you are able to proceed with this.

 

 

Thanks,

Arslan

EDing
Partner
172 Views

Hi Arslan,

 

Glad to see your answer here! Thanks! Attached is the log file, could you tell what's missing from the log please?

 

Best,

Ellen

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Hi Ellen,

 

I am looking at the log file, it is hard to pin point the exact issue. As I can see a couple of IP's been compiled in the design.

Is it possible to share the design in a private message may be to take a further look ?

 

Or you can point me what IP was instantiated at line number pointed in Error message.

 

* Error: (vsim-3935) ../../BSM_EPL_PCL_EGL.vhd(1316): Port 'A_OUT' not found in the connected module.

Also can you confirm if IP is generated in verilog or vhdl ?

 

Thanks,

Arslan

EDing
Partner
172 Views

Hi Arslan! I have opened a case 00398071, it would be great if you can help identify the problem. Thanks!​

172 Views

Hi Ellen, I have taken a look at the design, please add the following lines to you “BSM_EPL_PCL_EGL.vhd” file --edits for simulation library altera_mf; use altera_mf.all; library altera; use altera.all; Let me know if you are able to proceed with this. Thanks, Regards, Arslan
EDing
Partner
172 Views

Thumbs up to you again, Arslan!​

172 Views

Glad to know you are able to proceed with the suggested workaround.

 

Thanks,

Arslan

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